\begin{itemize}
\item We implemented a reduction circuit in \clash{}\pause
\item Simulation results in Haskell match VHDL simulation results\pause
\item Synthesis completes without errors or warnings\pause
\begin{itemize}
\item We implemented a reduction circuit in \clash{}\pause
\item Simulation results in Haskell match VHDL simulation results\pause
\item Synthesis completes without errors or warnings\pause