projects
/
matthijs
/
master-project
/
cλash.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Add clk port on any stateful entity.
[matthijs/master-project/cλash.git]
/
VHDL.hs
diff --git
a/VHDL.hs
b/VHDL.hs
index ef89c4a6dbcda9a592419b5e79aa40786651ee2b..ee61c500a6916f676fd75e1c7566d6d8bb868eab 100644
(file)
--- a/
VHDL.hs
+++ b/
VHDL.hs
@@
-58,7
+58,7
@@
createEntity hsfunc fdata =
(sigName info)
ty = sigTy info
(sigName info)
ty = sigTy info
--- | Create the VHDL AST for an entity
+
-- | Create the VHDL AST for an entity
createEntityAST ::
HsFunction -- | The signature of the function we're working with
-> [VHDLSignalMap] -- | The entity's arguments
createEntityAST ::
HsFunction -- | The signature of the function we're working with
-> [VHDLSignalMap] -- | The entity's arguments
@@
-71,9
+71,16
@@
createEntityAST hsfunc args res =
vhdl_id = mkEntityId hsfunc
ports = concatMap (mapToPorts AST.In) args
++ mapToPorts AST.Out res
vhdl_id = mkEntityId hsfunc
ports = concatMap (mapToPorts AST.In) args
++ mapToPorts AST.Out res
+ ++ clk_port
mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec]
mapToPorts mode m =
map (mkIfaceSigDec mode) (Foldable.toList m)
mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec]
mapToPorts mode m =
map (mkIfaceSigDec mode) (Foldable.toList m)
+ -- Add a clk port if we have state
+ clk_port = if hasState hsfunc
+ then
+ [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty]
+ else
+ []
-- | Create a port declaration
mkIfaceSigDec ::
-- | Create a port declaration
mkIfaceSigDec ::
@@
-230,6
+237,10
@@
getLibraryUnits (hsfunc, fdata) =
bit_ty :: AST.TypeMark
bit_ty = AST.unsafeVHDLBasicId "Bit"
bit_ty :: AST.TypeMark
bit_ty = AST.unsafeVHDLBasicId "Bit"
+-- | The VHDL std_logic
+std_logic_ty :: AST.TypeMark
+std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
+
-- Translate a Haskell type to a VHDL type
vhdl_ty :: Type.Type -> AST.TypeMark
vhdl_ty ty = Maybe.fromMaybe
-- Translate a Haskell type to a VHDL type
vhdl_ty :: Type.Type -> AST.TypeMark
vhdl_ty ty = Maybe.fromMaybe