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Add generated VHDL to the hardware description chapter.
[matthijs/master-project/report.git]
/
Outline
diff --git
a/Outline
b/Outline
index 7a183037c745ea4973829301a57d82d4be8bc08a..bbcf46ad914c0e12a0a8615ef1786b1ff3c53db7 100644
(file)
--- a/
Outline
+++ b/
Outline
@@
-41,15
+41,11
@@
Future work
* Multiple cycle descriptions
* Higher order state
* New language
* Multiple cycle descriptions
* Higher order state
* New language
-
Don't care
+
*
Don't care
TODO: Define user / developer
TODO: Define user / developer
-TODO: Comiler vs translator
TODO: Hardware description / model vs program
TODO: Hardware description / model vs program
-TODO: State & pattern matches
TODO: Separate compilation / Prelude
TODO: Separate compilation / Prelude
-TODO: Add case binder removal transformation
-TODO: Remove all "statement"s
TODO: User-defined type classes (future work?)
TODO: Entity / Architecture / Component vs Function?
TODO: Expand on "representable"
TODO: User-defined type classes (future work?)
TODO: Entity / Architecture / Component vs Function?
TODO: Expand on "representable"
@@
-58,6
+54,9
@@
TODO: Variable vs binder
TODO: simplification -> Normalisation?
TODO: Use saturated (application) instead of complete (application)?
TODO: core => Core
TODO: simplification -> Normalisation?
TODO: Use saturated (application) instead of complete (application)?
TODO: core => Core
-TODO: \defref{beta-reduction} -> \defref{β-reduction}
-TODO: Make interaction links not bold
TODO: Say something about implementation differences with transformation specs
TODO: Say something about implementation differences with transformation specs
+TODO: Say something about the builtin functions somewhere (ref: christiaan)
+TODO: Future work: Use Cλash
+TODO: Abstract
+TODO: Preface
+TODO: Top level function -> top level binder