+genMap :: BuiltinBuilder
+genMap = genVarArgs genMap'
+genMap' res f [mapped_f, arg] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!")
+ (Map.lookup mapped_f signatures)
+ let
+ -- Setup the generate scheme
+ len = (tfvec_len . Var.varType) res
+ label = mkVHDLExtId ("mapVector" ++ (varToString res))
+ nPar = AST.unsafeVHDLBasicId "n"
+ range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ genScheme = AST.ForGn nPar range
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar
+ outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
+ portassigns = Maybe.catMaybes [inport,outport]
+ -- Generate the portmap
+ mapLabel = "map" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
+ in
+ return $ [genSm]
+
+genZipWith :: BuiltinBuilder
+genZipWith = genVarArgs genZipWith'
+genZipWith' res f args@[zipped_f, arg1, arg2] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!")
+ (Map.lookup zipped_f signatures)
+ let
+ -- Setup the generate scheme
+ len = (tfvec_len . Var.varType) res
+ label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
+ nPar = AST.unsafeVHDLBasicId "n"
+ range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ genScheme = AST.ForGn nPar range
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) (varToVHDLId arg1) nPar
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId arg2) nPar
+ outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
+ in
+ return $ [genSm]
+
+genFoldl :: BuiltinBuilder
+genFoldl = genVarArgs genFoldl'
+genFoldl' resVal f [folded_f, startVal, inVec] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!")
+ (Map.lookup folded_f signatures)
+ let (vec, _) = splitAppTy (Var.varType inVec)
+ let vecty = Type.mkAppTy vec (Var.varType startVal)
+ vecType <- vhdl_ty vecty
+ -- Setup the generate scheme
+ let len = (tfvec_len . Var.varType) inVec
+ let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
+ let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
+ let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range
+ -- Make the intermediate vector
+ let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
+ -- Get the entity name and port names
+ let entity_id = ent_id entity
+ let argports = map (Monad.liftM fst) (ent_args entity)
+ let resport = (Monad.liftM fst) (ent_res entity)
+ -- Return the generate functions
+ let genSm = AST.GenerateSm genlabel genScheme []
+ [ AST.CSGSm (genFirstCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ , AST.CSGSm (genOtherCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ , AST.CSGSm (genLastCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ ]
+ return $ [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
+ where
+ genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ cellLabel = mkVHDLExtId "firstcell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElem (argports!!0) (varToString startVal)
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "othercell"
+ cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0"))
+ ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genLastCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "lastCell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1)))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Generate the output assignment
+ assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
+ (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)])))
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign]
+
+
+-- Returns the VHDLId of the vector function with the given name for the given
+-- element type. Generates -- this function if needed.
+vectorFunId :: Type.Type -> String -> VHDLSession AST.VHDLId
+vectorFunId el_ty fname = do
+ elemTM <- vhdl_ty el_ty
+ -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
+ -- the VHDLState or something.
+ let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
+ typefuns <- getA vsTypeFuns
+ case Map.lookup (OrdType el_ty, fname) typefuns of
+ -- Function already generated, just return it
+ Just (id, _) -> return id
+ -- Function not generated yet, generate it
+ Nothing -> do
+ let functions = genUnconsVectorFuns elemTM vectorTM
+ case lookup fname functions of
+ Just body -> do
+ modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, body)
+ return function_id
+ Nothing -> error $ "I don't know how to generate vector function " ++ fname