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Generate a VHDL architecture for each function.
[matthijs/master-project/cλash.git]
/
Flatten.hs
diff --git
a/Flatten.hs
b/Flatten.hs
index 15f99808600bb37cf2880405d48a3639dc78e478..cd515859f0879755d9d7f6e704bfb241271d9fbc 100644
(file)
--- a/
Flatten.hs
+++ b/
Flatten.hs
@@
-38,7
+38,7
@@
typeMapToUseMap ::
-> FlattenState (SignalMap UnnamedSignal)
typeMapToUseMap (Single ty) = do
-> FlattenState (SignalMap UnnamedSignal)
typeMapToUseMap (Single ty) = do
- id <- genSignalId
+ id <- genSignalId
ty
return $ Single id
typeMapToUseMap (Tuple tymaps) = do
return $ Single id
typeMapToUseMap (Tuple tymaps) = do
@@
-53,12
+53,12
@@
flattenFunction ::
flattenFunction _ (Rec _) = error "Recursive binders not supported"
flattenFunction hsfunc bind@(NonRec var expr) =
flattenFunction _ (Rec _) = error "Recursive binders not supported"
flattenFunction hsfunc bind@(NonRec var expr) =
- FlatFunction args res apps conds
+ FlatFunction args res apps conds
sigs
where
where
- init_state = ([], [], 0)
+ init_state = ([], [],
[],
0)
(fres, end_state) = State.runState (flattenExpr [] expr) init_state
(args, res) = fres
(fres, end_state) = State.runState (flattenExpr [] expr) init_state
(args, res) = fres
- (apps, conds, _) = end_state
+ (apps, conds,
sigs,
_) = end_state
flattenExpr ::
BindMap
flattenExpr ::
BindMap