{-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-}
module Main where
-import qualified Prelude as P
-{-# LINE 29 "PolyAlu.lhs" #-}
import CLasH.HardwareTypes
-{-# LINE 36 "PolyAlu.lhs" #-}
import CLasH.Translator.Annotations
-{-# LINE 48 "PolyAlu.lhs" #-}
-type Op s a = a -> Vector s a -> a
-type Opcode = Bit
-{-# LINE 56 "PolyAlu.lhs" #-}
-type RegBank s a = Vector (s :+: D1) a
-type RegState s a = State (RegBank s a)
-{-# LINE 64 "PolyAlu.lhs" #-}
-type Word = SizedInt D12
-{-# LINE 76 "PolyAlu.lhs" #-}
-primOp :: (a -> a -> a) -> Op s a
-primOp f a b = a `f` a
-{-# LINE 84 "PolyAlu.lhs" #-}
-vectOp :: (a -> a -> a) -> Op s a
-vectOp f a b = foldl f a b
-{-# LINE 99 "PolyAlu.lhs" #-}
+import qualified Prelude as P
+{-# LINE 52 "PolyAlu.lhs" #-}
+type Op a = a -> a -> a
+type Opcode = Bit
+{-# LINE 60 "PolyAlu.lhs" #-}
+type RegBank s a =
+ Vector (s :+: D1) a
+type RegState s a =
+ State (RegBank s a)
+{-# LINE 68 "PolyAlu.lhs" #-}
+type Word = SizedInt D12
+{-# LINE 88 "PolyAlu.lhs" #-}
alu ::
- Op s a ->
- Op s a ->
- Opcode -> a -> Vector s a -> a
+ Op a -> Op a ->
+ Opcode -> a -> a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
+{-# LINE 110 "PolyAlu.lhs" #-}
+registers ::
+ ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s ->
+ RangedWord s -> (RegState s a) -> (RegState s a, a )
{-# LINE 118 "PolyAlu.lhs" #-}
-registerBank ::
- ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
- RangedWord s -> Bit -> ((RegState s a), a )
-
-registerBank (State mem) data_in rdaddr wraddr wrenable =
+registers data_in rdaddr wraddr (State mem) =
((State mem'), data_out)
where
- data_out = mem!rdaddr
- mem' | wrenable == Low = mem
- | otherwise = replace mem wraddr data_in
-{-# LINE 141 "PolyAlu.lhs" #-}
-{-# ANN actual_cpu TopEntity#-}
-actual_cpu ::
- (Opcode, Word, Vector D4 Word, RangedWord D9,
- RangedWord D9, Bit) -> RegState D9 Word ->
- (RegState D9 Word, Word)
+ data_out = mem!rdaddr
+ mem' = replace mem wraddr data_in
+{-# LINE 138 "PolyAlu.lhs" #-}
+type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9)
+{-# LINE 142 "PolyAlu.lhs" #-}
+{-# ANN cpu TopEntity#-}
+cpu ::
+ Instruction -> RegState D9 Word -> (RegState D9 Word, Word)
-actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
+cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out)
where
- alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
- (ram',ram_out) = registerBank ram a rdaddr wraddr wren
-{-# LINE 160 "PolyAlu.lhs" #-}
+ alu_out = alu (+) (-) opc d ram_out
+ (ram',ram_out) = registers alu_out rdaddr wraddr ram
+{-# LINE 165 "PolyAlu.lhs" #-}
{-# ANN initstate InitState#-}
initstate :: RegState D9 Word
initstate = State (copy (0 :: Word))
{-# ANN program TestInput#-}
-program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)]
+program :: [Instruction]
program =
- [ (Low, 4, copy (0::Word), 0, 0, High) -- Write 4 to Reg0, out = 0
- , (Low, 3, copy (0::Word), 0, 1, High) -- Write 3 to Reg1, out = Reg0 + Reg0 = 8
- , (High,0, copy (3::Word), 1, 0, Low) -- No Write , out = 15
+ [ (Low, 4, 0, 0) -- Write 4 to Reg0
+ , (Low, 3, 0, 1) -- Write 3+4 to Reg1
+ , (High,8, 1, 2) -- Write 8-7 to Reg2
]
run func state [] = []
main = do
let input = program
let istate = initstate
- let output = run actual_cpu istate input
- mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output
+ let output = run cpu istate input
+ mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output
return ()