-Implementation issues
+Context
+ Other FHDLs (short, Christiaan has details)
+
+ Advantages of clash / why clash?
+
+ VHDL / Verilog / EDIF etc. Why VHDL?
+
-State
+Haskell as hardware
+ Simple function -> component interpretation (Model: Structure)
+ Model: State
+ Explicit vs implicit passing of state (e.g, delay)
+ Explicit vs implicit marking
+ Interpret: Polymorphism
+ Interpret: Higher order
+ Need: Dependent types
+ Impossible things: Infinite recursion, higher order expressions,
+ recursive types.
Prototype
+ Choice of Haskell
+ Core - description of the language (appendix?)
Stages (-> Core, Normalization, -> VHDL)
+ Implementation issues
-Core
-
-VHDL vs EDIF generation
+ Haskell language coverage / constraints
+ Recursion
+ Builtin types
+ Custom types (Sum types, product types)
+ Function types / higher order expressions
Normalization
Normal form
Rules used
Completeness / conditions on input
Termination
- Casts
-
-Context
-
-Other FHDLs
-
-VHDL / Verilog / EDIF etc.
-
-Advantages of clash / why clash?
-
-Haskell as hardware
- Dependent types
- Impossible things: Infinite recursion, higher order expressions
-
-Haskell language coverage / constraints
- Recursion
- Builtin types
- Custom types (Sum types, product types)
- Function types / higher order expressions
+ Casts / Strictness / Casebinders not fully supported
Future work
Boilerplate reduction (State distribution & pipelining)
Recursion
- Multiple time domains
+ Multiple time domains (Events) -- Also, clock line optimization /
+ -- write enable
Multiple cycle descriptions
+ Higher order state
+ New language