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23 \title{Haskell-ish Hardware Descriptions}
24 \author{Matthijs Kooijman, Christiaan Baaij, Jan Kuper}
25 \date{Dutch Haskell user group day, 2010}
29 \section{Introduction}
35 \item Master's thesis - hardware description language \& compiler Cλash
36 \item Short introduction, then examples
37 \item VHDL is common, but sucks
38 \item Cλash compiler is not embedded, but external
45 \includegraphics[width=10cm]{figures/pipeline}
51 \item Working prototype, rough edges
53 \item Custom normalization - Reduction system of transformations
54 \item Simple subset of VHDL - existing tooling
61 \frametitle{Multiply-accumulate}
64 mac :: Num a => a -> a -> a -> a
69 type Word = SizedWord D16
70 mac :: Word -> Word -> Word -> Word
74 mac x y acc = acc + x * y
77 \includegraphics[width=6cm]{figures/mac}
82 \item functions are components (operators are functions too!)
83 \item function application is component instantiation
84 \item Polymorphic description
85 \item But top level must be monomorphic (next frame)
90 \frametitle{Stateful multiply-accumulate}
92 newtype State a = State a
94 smac :: State Word -> Word -> Word -> (State Word, Word)
95 smac (State s) x y = (State s', s')
99 \includegraphics[width=6cm]{figures/smac}
104 \item State is explicit: Argument and result
105 \item Produces register == memory
110 \frametitle{Simple CPU}
111 \includegraphics[width=11cm]{figures/cpu}
116 \item Simple CPU: Instructions are one opcode and four address pairs
117 \item One input line, one output line, no memories
118 \item Small, but basis for real hardware
119 \item Three fixed function units, one multipurpose function unit
124 \frametitle{Fixed function function units}
126 fu :: (... u ~ n :-: D1 ...) => (a -> a -> t)
128 -> (Index u, Index u)
131 fu op inputs (a1, a2) = op (inputs!a1) (inputs!a2)
144 \item fu abstracts the input selection
145 \item fu takes an arbitrary binary operation
146 \item Some context left out
147 \item Vector is a fixed size vector, Index an index
152 \frametitle{Multi-purpose function unit}
154 data Opcode = Shift | Xor | Equal
156 multiop :: Opcode -> Word -> Word -> Word
157 multiop Shift = shift
159 multiop Equal = \a b -> if a == b then 1 else 0
164 fu0 c = fu (multiop c)
170 \item multiop takes an opcode and produces a binary operation
171 \item multiop is partially applied to the opcode
176 \frametitle{The complete CPU}
178 type CpuState = State (Vector D4 Word)
181 -> (Word, Opcode, Vector D4 (Index D6, Index D6))
183 cpu (State s) (x, opc, addrs) = (State s', out)
185 inputs = x +> (0 +> (1 +> s))
186 s' = (fu0 opc inputs (addrs!(0 :: Index D3))) +> (
187 (fu1 inputs (addrs!(1 :: Index D3))) +> (
188 (fu2 inputs (addrs!(2 :: Index D3))) +> (
189 (fu3 inputs (addrs!(3 :: Index D3))) +> (
196 \item Uses partial application for fu0
197 \item Cpu state is one register per fu
202 \frametitle{Floating point reduction circuit}
203 \includegraphics[width=11cm]{figures/reducer}
207 \item Sums rows of corresponding FP numbers (e.g., sparse matrix
209 \item Complexity: Pipelined adder, multiple rows simultaneously
210 \item Big design, implemented in Cλash
215 \frametitle{Controller function}
217 controller (inp1, inp2, pT, from_res_mem) =
218 (arg1, arg2, shift, to_res_mem)
220 (arg1, arg2, shift, to_res_mem)
221 | valid pT && valid from_res_mem
222 = (pT , from_res_mem , 0, False)
223 | valid pT && valid inp1 && discr pT == discr inp1
224 = (pT , inp1 , 1, False)
225 | valid inp1 && valid inp2 && discr inp1 == discr inp2
226 = (inp1 , inp2 , 2, valid pT)
228 = (inp1 , (True, (0, discr inp1)) , 1, valid pT)
230 = (notValid, notValid , 0, valid pT)
236 \item Elegant implementation of algorithm rules
244 \frametitle{Future work}
246 \item More systematic normalization
247 \item Recursion / normal lists
248 \item Nested state abstraction
249 \item Multiple clock domains / asynchronicity
250 \item Graphical output
256 \item More systematic normalization - proofs
257 \item Recursion / normal lists - Fixed size recursion has problems
258 \item Nested state abstraction - Larger designs can get messy
259 \item Multiple clock domains / asynchronicity - Clock is currently implicit
260 \item Graphical output - For analysis and testing
261 \item Plenty of assignments!
268 \vspace{2cm}\centerline{\Huge{Thanks!}}
270 http://wwwhome.cs.utwente.nl/~baaijcpr/ClaSH/Index.html
271 \begin{center}or just\end{center}
272 http://google.com/search?q={\bf{}C$\lambda$aSH}\&btnI=I'm Feeling Lucky
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