1 \section{Real Hardware Designs}
3 \frametitle{More than just toys}
6 \item We designed a reduction circuit in \clash{}\pause
7 \item Simulation results in Haskell match VHDL simulation results\pause
8 \item Synthesis completes without errors or warnings\pause
9 \item For the same Virtex-4 FPGA: \pause
11 \item Hand coded VHDL design runs at 200 MHz\pause
12 \item \clash{} design runs at around 85* MHz
16 \uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
18 \item Toys like the poly cpu one are good to give a quick demo
19 \item But we used \clash{} to design 'real' hardware
20 \item Reduction circuit sums the numbers in a row of a (sparse) matrix
21 \item Nice speed considering we don't optimize for it
26 \includegraphics[height=\paperheight]{reducerschematic.png}