1 \section{Real Hardware Designs}
3 \frametitle{More than just toys}
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12 \item We implemented a reduction circuit in \clash{}\pause
13 \item Simulated in Haskell. VHDL simulation results match\pause
14 \item Synthesis completes without errors or warnings\pause
15 \item Around half speed of handcoded and optimized VHDL
19 \item Toys like the poly cpu one are good to give a quick demo
20 \item But we used \clash{} to design 'real' hardware
21 \item Reduction circuit sums the numbers in a row, of different length
22 \item It uses a pipelined adder: multiple rows in pipeline, rows longer than pipeline
23 \item We hope you see this is not a trivial problem
24 \item Nice speed considering we don't optimize for it (only single example!)
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29 % \includegraphics[height=\paperheight]{reducerschematic.png}