1 % This file was created with JabRef 2.4.2.
5 author = {Bjesse, Per and Claessen, Koen and Sheeran, Mary and Singh, Satnam},
6 title = {{Lava: hardware design in Haskell}},
7 booktitle = {{ICFP '98: Proceedings of the third ACM SIGPLAN international conference
8 on Functional programming}},
11 address = {New York, NY, USA},
13 doi = {http://doi.acm.org/10.1145/289423.289440},
14 isbn = {1-58113-024-4},
15 location = {Baltimore, Maryland, United States},
17 timestamp = {2010.01.20}
21 author = {Byron Cook and John Launchbury and John Matthews},
22 title = {{Specifying superscalar microprocessors in Hawk}},
23 booktitle = {{Formal Techniques for Hardware and Hardware-like Systems}},
26 timestamp = {2010.01.20}
30 author = {Jones, G. and Sheeran, M.},
31 title = {{Circuit Design in Ruby}},
32 booktitle = {{Formal Methods for VLSI Design}},
34 address = {Lyngby, Denmark},
35 publisher = {Elsevier Science Publishers},
36 citeulike-article-id = {304676},
37 journal = {Circuit Design in Ruby},
40 posted-at = {2005-08-26 18:08:07},
42 timestamp = {2010.01.20}
46 author = {Yanbing Li and Leeser, M.},
47 title = {{HML, a novel hardware description language and its translation to
49 journal = {{Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}},
55 doi = {10.1109/92.820756},
57 keywords = {ML language, hardware description languages, type theoryHML, SML functional
58 programming language, VHDL translation, digital design, hardware
59 description language, polymorphic type, translator, type checker,
62 timestamp = {2010.01.20}
66 author = {Yanbing Li and Leeser, M.},
67 title = {{HML: an innovative hardware description language and its translation
69 booktitle = {{Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL
70 '95/VLSI '95., IFIP International Conference on Hardware Description
71 Languages; IFIP International Conference on Very Large Scale Integration.,
72 Asian and South Pacific}},
76 doi = {10.1109/ASPDAC.1995.486388},
77 keywords = {abstract data types, functional languages, functional programming,
78 hardware description languagesHML, VHDL, advanced type checking,
79 functional programming language, hardware description language, polymorphic
80 types, type inference},
82 timestamp = {2010.01.20}
86 author = {Matthews, J. and Cook, B. and Launchbury, J.},
87 title = {{Microprocessor specification in Hawk}},
88 booktitle = {{Proceedings of 1998 International Conference on Computer Languages}},
92 abstract = {Modern microprocessors require an immense investment of time and effort
93 to create and verify, from the high level architectural design downwards.
94 We are exploring ways to increase the productivity of design engineers
95 by creating a domain specific language for specifying and simulating
96 processor architectures. We believe that the structuring principles
97 used in modern functional programming languages, such as static typing,
98 parametric polymorphism, first class functions, and lazy evaluation
99 provide a good formalism for such a domain specific language, and
100 have made initial progress by creating a library on top of the functional
101 language Haskell. We have specified the integer subset of an out
102 of order, superscalar DLX microprocessor, with register renaming,
103 a reorder buffer, a global reservation station, multiple execution
104 units, and speculative branch execution. Two key abstractions of
105 this library are the signal abstract data type (ADT), which models
106 the simulation history of a wire, and the transaction ADT, which
107 models the state of an entire instruction as it travels through the
109 doi = {10.1109/ICCL.1998.674160},
111 keywords = {abstract data types, formal specification, functional languages, functional
112 programming, hardware description languages, microprocessor chips,
113 software librariesHawk language, design engineers, domain specific
114 language, first class functions, functional language Haskell, functional
115 programming languages, global reservation station, high level architectural
116 design, integer subset, lazy evaluation, microprocessor specification,
117 multiple execution units, out of order superscalar DLX microprocessor,
118 parametric polymorphism, processor architecture simulation, register
119 renaming, reorder buffer, signal abstract data type, simulation history,
120 software library, speculative branch execution, static typing,, structuring
121 principles, transaction ADT},
123 timestamp = {2010.01.20}
126 @INPROCEEDINGS{ForSyDe,
127 author = {Sander, Ingo and Jantsch, Axel},
128 title = {{Transformation based communication and clock domain refinement for
130 booktitle = {{DAC '02: Proceedings of the 39th annual Design Automation Conference}},
133 address = {New York, NY, USA},
135 doi = {http://doi.acm.org/10.1145/513918.513992},
136 isbn = {1-58113-461-4},
137 location = {New Orleans, Louisiana, USA},
139 timestamp = {2010.01.20}
143 author = {Sheeran, Mary},
144 title = {{$\mu$FP, a language for VLSI design}},
145 booktitle = {{LFP '84: Proceedings of the 1984 ACM Symposium on LISP and functional
149 address = {New York, NY, USA},
151 doi = {http://doi.acm.org/10.1145/800055.802026},
152 isbn = {0-89791-142-3},
153 location = {Austin, Texas, United States},
155 timestamp = {2010.01.20}
159 title = {{VHDL Language Reference Manual}},
160 organization = {IEEE},
161 number = {1076-2008},
164 timestamp = {2009.11.17}
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