6 * Other FHDLs (short, Christiaan has details)
7 * Advantages of clash / why clash?
10 * Simple function -> component interpretation (Model: Structure)
15 * Explicit vs implicit passing of state (e.g, delay)
16 * Explicit vs implicit marking
17 * Interpret: Polymorphism
18 * Interpret: Higher order
23 * VHDL / Verilog / EDIF etc. Why VHDL?
24 * Stages (-> Core, Normalization, -> VHDL)
25 . Core - description of the language
28 Implementation issues -- Which?
34 . Properties / Proofs (termination, soundness, completeness, determinism)
35 Casts / Strictness / Casebinders not fully supported
38 . Boilerplate reduction (State distribution & pipelining)
40 * Multiple time domains (Events) -- Also, clock line optimization /
42 * Multiple cycle descriptions
47 TODO: Define user / developer
48 TODO: Comiler vs translator
49 TODO: Hardware description / model vs program
50 TODO: State & pattern matches