6 Stages (-> Core, Normalization, -> VHDL)
10 VHDL vs EDIF generation
15 Completeness / conditions on input
23 VHDL / Verilog / EDIF etc.
25 Advantages of clash / why clash?
29 Impossible things: Infinite recursion, higher order expressions
31 Haskell language coverage / constraints
34 Custom types (Sum types, product types)
35 Function types / higher order expressions
38 Boilerplate reduction (State distribution & pipelining)
41 Multiple cycle descriptions