* Keep track of the current stage number (not montiumcc compatible) so we

[matthijs/projects/montium-fft.git] / FFT.mc

diff --git a/FFT.mc b/FFT.mc
index 3ad081668c51b058cece7d041f772a5c415ad94c..626b0dc51508f41d2eff5804bed7b8ac8f2537a7 100644 (file)
--- a/FFT.mc
+++ b/FFT.mc
@@ -6,6 +6,7 @@
 \r
 #include "FFT.h"\r
 \r
 \r
 #include "FFT.h"\r
 \r

+int stage = 1;\r

 /**\r
  * Executes a single butterfly on ALU 0-3. The inputs are the words taken from\r
  * in, which will be read on various inputs of ALU 0-3. Outputs will be\r
 /**\r
  * Executes a single butterfly on ALU 0-3. The inputs are the words taken from\r
  * in, which will be read on various inputs of ALU 0-3. Outputs will be\r


@@ -98,7 +99,13 @@ INLINE struct bf_in read_input_regular(struct mems m, bool cycle_odd, bool stage
        add_offset(m.input_a_im, 1);\r
        add_offset(m.input_b_re, 1);\r
        add_offset(m.input_b_im, 1);\r
        add_offset(m.input_a_im, 1);\r
        add_offset(m.input_b_re, 1);\r
        add_offset(m.input_b_im, 1);\r

-       /* TODO: Update twiddle offsets */\r
+       \r
+       /* TODO: Is this true? */\r
+       add_offset(m.twiddle_re, (PARAM_N_t>>stage));\r
+       add_offset(m.twiddle_im, (PARAM_N_t>>stage));\r
+       use_mask(m.twiddle_re, (PARAM_N_t/2)-1);\r
+       use_mask(m.twiddle_im, (PARAM_N_t/2)-1);\r
+\r

        return in;\r
 }\r
 \r
        return in;\r
 }\r
 \r


@@ -256,11 +263,13 @@ void run() {
                next_cycle();\r
                do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF);\r
                do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF);\r
                next_cycle();\r
                do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF);\r
                do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF);\r

+               stage++;\r

                next_cycle();\r
                init_input_addresses_regular(m, ODD_STAGE);\r
                m = init_mem_mapping(ODD_STAGE);\r
                next_cycle();\r
                do_half_regular_stage(m, ODD_STAGE, FIRST_HALF);\r
                do_half_regular_stage(m, ODD_STAGE, SECOND_HALF);\r
                next_cycle();\r
                init_input_addresses_regular(m, ODD_STAGE);\r
                m = init_mem_mapping(ODD_STAGE);\r
                next_cycle();\r
                do_half_regular_stage(m, ODD_STAGE, FIRST_HALF);\r
                do_half_regular_stage(m, ODD_STAGE, SECOND_HALF);\r

+               stage++;\r

        } while (loop_next(LC1));\r
 }\r
        } while (loop_next(LC1));\r
 }\r