From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Fri, 30 Oct 2009 10:08:48 +0000 (+0100)
Subject: Add some extra outline to the Hardware Description chapter.
X-Git-Tag: final-thesis~187
X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=commitdiff_plain;h=c9258d5e0a89adb2f9f87ce5c668ba2a561d6bf3

Add some extra outline to the Hardware Description chapter.
---

diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex
index e117886..644ce01 100644
--- a/Chapters/Prototype.tex
+++ b/Chapters/Prototype.tex
@@ -50,6 +50,9 @@
 
     TODO: Was Haskell really a good choice? Perhaps say this somewhere else?
 
+    \subsection{Output language or format}
+        VHDL / Verilog / EDIF etc. Why VHDL?
+
   \section{Prototype design}
     As stated above, we will use the Glasgow Haskell Compiler (\small{GHC}) to
     implement our prototype compiler. To understand the design of the
@@ -710,9 +713,8 @@ fstint = λa.λb.fst @Int @Int a b
           \subsection[sec:prototype:separate]{Separate compilation}
           - Simplified core?
 
-        Haskell language coverage / constraints
-                Recursion
-                Builtin types
-                Custom types (Sum types, product types)
-                Function types / higher order expressions
-
+  \section{Haskell language coverage and constraints}
+    Recursion
+    Builtin types
+    Custom types (Sum types, product types)
+    Function types / higher order expressions