From: Matthijs Kooijman Date: Wed, 11 Nov 2009 10:15:56 +0000 (+0100) Subject: Update outline. X-Git-Tag: final-thesis~159 X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=commitdiff_plain;h=a472d8d94908d8f466a4cafe4d55c4c9410161d8;hp=752dbf1d4d824b3278df4f71b496e99f5cb0b2b1 Update outline. --- diff --git a/Chapters/HardwareDescription.tex b/Chapters/HardwareDescription.tex index ddce85d..9e4061c 100644 --- a/Chapters/HardwareDescription.tex +++ b/Chapters/HardwareDescription.tex @@ -244,7 +244,7 @@ and3 a b c = and (and a b) c the prototype, which uses \emph{type families}. \stopdesc - TODO: Reference Christiaan + TODO: Reference Christiaan / describe dependent typing \subsection{User-defined types} There are three ways to define new types in Haskell: Algebraic datatypes with the \hs{data} keyword, type synonyms with the \hs{type} diff --git a/Outline b/Outline index 074f6a6..88cc626 100644 --- a/Outline +++ b/Outline @@ -8,32 +8,26 @@ Introduction Haskell as hardware * Simple function -> component interpretation (Model: Structure) +* Choice / Case +* Types * Partial application * Model: State * Explicit vs implicit passing of state (e.g, delay) * Explicit vs implicit marking * Interpret: Polymorphism * Interpret: Higher order - Need: Dependent types * Recursion - Impossible things: Infinite recursion, higher order expressions, - recursive types, ... Prototype * Choice of Haskell - VHDL / Verilog / EDIF etc. Why VHDL? +* VHDL / Verilog / EDIF etc. Why VHDL? * Stages (-> Core, Normalization, -> VHDL) -. Core - description of the language (appendix?) +. Core - description of the language +* Expressions + Typing Implementation issues -- Which? State annotations - Haskell language coverage / constraints - Recursion - Builtin types - Custom types (Sum types, product types) - Function types / higher order expressions - State type -> Anything representable - Normalization * Normal form * Rules used @@ -48,5 +42,9 @@ Future work * Multiple cycle descriptions * Higher order state * New language + Don't care TODO: Define user / developer +TODO: Comiler vs translator +TODO: Hardware description / model vs program +TODO: State & pattern matches