From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Mon, 30 Nov 2009 20:45:34 +0000 (+0100)
Subject: Put a VHDL in smallcaps.
X-Git-Tag: final-thesis~134
X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=commitdiff_plain;h=70c17aa5346776371e1d66ecc0371c0a3ce179d2;hp=a117295a33890774410292246ae8d21bd2505cf8

Put a VHDL in smallcaps.
---

diff --git a/Chapters/Future.tex b/Chapters/Future.tex
index 852d14f..9c60dfe 100644
--- a/Chapters/Future.tex
+++ b/Chapters/Future.tex
@@ -391,8 +391,8 @@ behaviour is not needed.
 
 The main cost of this approach will probably be extra complexity in the
 compiler: The paths (state) data can take become very non-trivial, and it
-is probably hard to properly analyze these paths and produce the intended VHDL
-description.
+is probably hard to properly analyze these paths and produce the
+intended \VHDL description.
 
 \section{Multiple cycle descriptions}
 In the current Cλash prototype, every description is a single-cycle