From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Mon, 5 Oct 2009 12:15:42 +0000 (+0200)
Subject: Vertically center the register output port.
X-Git-Tag: final-thesis~223
X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=commitdiff_plain;h=18e247310fe31a0ab3696ee0f110cc078df0e132

Vertically center the register output port.
---

diff --git a/Utils/Metapost.tex b/Utils/Metapost.tex
index fd21385..63b0620 100644
--- a/Utils/Metapost.tex
+++ b/Utils/Metapost.tex
@@ -50,7 +50,8 @@ vardef newReg@#(expr v) text options=
       "xpart @#out = xpart @#e",
       "xpart @#d = xpart @#ck = xpart @#w",
     fi
-    "ypart @#d = ypart @#out = ypart (@#sw * .25 + @#nw * .75)",
+    "ypart @#out = ypart midpoint(@#n, @#s)",
+    "ypart @#d = ypart (@#sw * .25 + @#nw * .75)",
     "ypart @#ck = ypart (@#sw * .75 + @#nw * .25)";
 
   StandardTies;