X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Outline;h=56fc5f0eed03618e10990b71c28053999b28a9b0;hp=8b991c6bcd0eb3ffd85a9ef6fe797bee5d58ae44;hb=05ab912a6a0d53892521265750b313126ab442af;hpb=f227bf907ef2a55cfa824034f7db140c98c3225e

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-Context
-  Other FHDLs (short, Christiaan has details)
-
-  Advantages of clash / why clash?
-
-  VHDL / Verilog / EDIF etc. Why VHDL?
+Introduction
+*       Goals
+*       Outline
 
+*Context
+*       Other FHDLs (short, Christiaan has details)
+*       Advantages of clash / why clash?
 
 Haskell as hardware
-        Simple function -> component interpretation (Model: Structure)
-        Model: State
-          Explicit vs implicit passing of state (e.g, delay)
-          Explicit vs implicit marking
-        Interpret: Polymorphism
-        Interpret: Higher order
-	Need: Dependent types
-	Impossible things: Infinite recursion, higher order expressions,
-        recursive types.
+*       Simple function -> component interpretation (Model: Structure)
+*       Choice / Case
+*       Types
+*       Partial application
+*       Model: State
+*         Explicit vs implicit passing of state (e.g, delay)
+*         Explicit vs implicit marking
+*       Interpret: Polymorphism
+*       Interpret: Higher order
+*       Recursion
 
 Prototype
-        Choice of Haskell
-        Core - description of the language (appendix?)
-	Stages (-> Core, Normalization, -> VHDL)
-        Implementation issues
-
-        Haskell language coverage / constraints
-                Recursion
-                Builtin types
-                Custom types (Sum types, product types)
-                Function types / higher order expressions
+*       Choice of Haskell
+*       VHDL / Verilog / EDIF etc. Why VHDL?
+*	Stages (-> Core, Normalization, -> VHDL)
+.       Core - description of the language
+*         Expressions
+          Typing
+        Implementation issues -- Which?
+        State annotations
 
 Normalization
-	Normal form
-	Rules used
-	Completeness / conditions on input
-	Termination
-	Casts / Strictness / Casebinders not fully supported
+*	Normal form
+*	Rules used
+.	Properties / Proofs (termination, soundness, completeness, determinism)
 
 Future work
-	Boilerplate reduction (State distribution & pipelining)
-	Recursion
-        Multiple time domains (Events) -- Also, clock line optimization /
+*	Boilerplate reduction (State distribution & pipelining)
+*	Recursion
+*       Multiple time domains (Events) -- Also, clock line optimization /
                                        -- write enable
-	Multiple cycle descriptions
-        Higher order state
-        New language
+*	Multiple cycle descriptions
+*       Higher order state
+*       New language
+*       Don't care
+
+TODO: Define user / developer
+TODO: Hardware description / model vs program
+TODO: Separate compilation / Prelude
+TODO: User-defined type classes (future work?)
+TODO: Entity / Architecture / Component vs Function?
+TODO: Expand on "representable"
+TODO: Register
+TODO: Variable vs binder
+TODO: simplification -> Normalisation?
+TODO: Use saturated (application) instead of complete (application)?
+TODO: core => Core
+TODO: Say something about implementation differences with transformation specs
+TODO: Say something about the builtin functions somewhere (ref: christiaan)
+TODO: Future work: Use Cλash
+TODO: Abstract
+TODO: Preface
+TODO: Footnote font has not lambda
+TODO: eta-abstraction -> expansion
+TODO: Top level function -> top level binder