X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Outline;h=074f6a6105a1ee1b20fa1944352d8f685b5717df;hp=73246f9dc78177926933e61cfeb46677cee82dea;hb=72edba19e4b745b8aa064ebd4f105d01a6055d8b;hpb=c8b72a250403339e3782e3efebc02a11f2411182

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+++ b/Outline
@@ -1,41 +1,52 @@
-Implementation issues
+Introduction
+*       Goals
+*       Outline
 
-State
+*Context
+*       Other FHDLs (short, Christiaan has details)
+*       Advantages of clash / why clash?
 
-Prototype
-	Stages (-> Core, Normalization, -> VHDL)
-
-Core
+Haskell as hardware
+*       Simple function -> component interpretation (Model: Structure)
+*       Partial application
+*       Model: State
+*         Explicit vs implicit passing of state (e.g, delay)
+*         Explicit vs implicit marking
+*       Interpret: Polymorphism
+*       Interpret: Higher order
+	Need: Dependent types
+*       Recursion
+	Impossible things: Infinite recursion, higher order expressions,
+                           recursive types, ...
 
-VHDL vs EDIF generation
+Prototype
+*       Choice of Haskell
+        VHDL / Verilog / EDIF etc. Why VHDL?
+*	Stages (-> Core, Normalization, -> VHDL)
+.       Core - description of the language (appendix?)
+        Implementation issues -- Which?
+        State annotations
+
+        Haskell language coverage / constraints
+                Recursion
+                Builtin types
+                Custom types (Sum types, product types)
+                Function types / higher order expressions
+                State type -> Anything representable
 
 Normalization
-	Normal form
-	Rules used
-	Completeness / conditions on input
-	Termination
-	Casts
-
-Context
-
-Other FHDLs
-
-VHDL / Verilog / EDIF etc.
-
-Advantages of clash / why clash?
-
-Haskell as hardware
-	Dependent types
-	Impossible things: Infinite recursion, higher order expressions
-
-Haskell language coverage / constraints
-	Recursion
-	Builtin types
-	Custom types (Sum types, product types)
-	Function types / higher order expressions
+*	Normal form
+*	Rules used
+.	Properties / Proofs (termination, soundness, completeness, determinism)
+	Casts / Strictness / Casebinders not fully supported
 
 Future work
-	Boilerplate reduction (State distribution & pipelining)
-	Recursion
-	Multiple time domains
-	Multiple cycle descriptions
+.	Boilerplate reduction (State distribution & pipelining)
+*	Recursion
+*       Multiple time domains (Events) -- Also, clock line optimization /
+                                       -- write enable
+*	Multiple cycle descriptions
+*       Higher order state
+*       New language
+
+TODO: Define user / developer