X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FPrototype.tex;h=3d8fb678c23406138162f1ac3fdc4affb5ccc21b;hp=e5cbb9df65b536214816eed6a2808359e7d86f90;hb=75d1001c7a7809c80bc4113477ad90b12f23b80f;hpb=747c2ba3d485fb5c3543e9435fbd3dff59ddb3f8 diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex index e5cbb9d..3d8fb67 100644 --- a/Chapters/Prototype.tex +++ b/Chapters/Prototype.tex @@ -53,11 +53,17 @@ lots of work!), using an existing language is the obvious choice. This also has the advantage that a large set of language features is available to experiment with and it is easy to find which features apply well and - which do not. A possible second prototype could use a custom language with - just the useful features (and possibly extra features that are specific to + which do not. Another import advantage of using an existing language, is + that simulation of the code becomes trivial. Since there are existing + compilers and interpreters that can run the hardware description directly, + it can be simulated without also having to write an interpreter for the + new language. + + A possible second prototype could use a custom language with just the useful + features (and possibly extra features that are specific to the domain of hardware description as well). - The second choice is which of the many existing languages to use. As + The second choice to be made is which of the many existing languages to use. As mentioned before, the chosen language is Haskell. This choice has not been the result of a thorough comparison of languages, for the simple reason that the requirements on the language were completely unclear at the start of @@ -85,14 +91,14 @@ \small{EDIF} standard. \cite[li89] This means that when working with \small{EDIF}, our prototype would become - technology dependent (\eg only work with \small{FPGA}s of a specific + technology dependent (\eg\ only work with \small{FPGA}s of a specific vendor, or even only with specific chips). This limits the applicability of our prototype. Also, the tools we would like to use for verifying, simulating and draw pretty pictures of our output (like Precision, or QuestaSim) are designed for \small{VHDL} or Verilog input. For these reasons, we will not use \small{EDIF}, but \small{VHDL} as our - output language. We choose \VHDL over Verilog simply because we are + output language. We choose \VHDL\ over Verilog simply because we are familiar with \small{VHDL} already. The differences between \small{VHDL} and Verilog are on the higher level, while we will be using \small{VHDL} mainly to write low level, netlist-like descriptions anyway. @@ -104,16 +110,47 @@ could achieve a similar amount of optimization in our prototype (nor should it be a goal, considering this is just a prototype). + \placeintermezzo{}{ + \startframedtext[width=8cm,background=box,frame=no] + \startalignment[center] + {\tfa Translation vs. compilation vs. synthesis} + \stopalignment + \blank[medium] + In this thesis the words \emph{translation}, \emph{compilation} and + sometimes \emph{synthesis} will be used interchangedly to refer to the + process of translating the hardware description from the Haskell + language to the \VHDL\ language. + + Similarly, the prototype created is referred to as both the + \emph{translator} as well as the \emph{compiler}. + + The final part of this process is usually referred to as \emph{\VHDL\ + generation}. + \stopframedtext + } + Note that we will be using \small{VHDL} as our output language, but will not use its full expressive power. Our output will be limited to using simple, structural descriptions, without any complex behavioural descriptions like arbitrary sequential statements (which might not be supported by all tools). This ensures that any tool that works - with \VHDL will understand our output (most tools do not support + with \VHDL\ will understand our output (most tools do not support synthesis of more complex \VHDL). This also leaves open the option to switch to \small{EDIF} in the future, with minimal changes to the prototype. + \section{Simulation and synthesis} + As mentioned above, by using the Haskell language, we get simulation of + our hardware descriptions almost for free. The only thing that is needed + is to provide a Haskell implementation of all built-in functions that can + be used by the Haskell interpreter to simulate them. + + The main topic of this thesis is therefore the path from the Haskell + hardware descriptions to \small{FPGA} synthesis, focusing of course on the + \VHDL\ generation. Since the \VHDL\ generation process preserves the meaning + of the Haskell description exactly, any simulation done in Haskell + \emph{should} produce identical results as the synthesized hardware. + \section[sec:prototype:design]{Prototype design} As suggested above, we will use the Glasgow Haskell Compiler (\small{GHC}) to implement our prototype compiler. To understand the design of the @@ -202,8 +239,15 @@ reason, \small{GHC} runs its simplifications and optimizations on the core representation as well \cite[jones96]. - However, we will use the normal core representation, not the simplified - core. Reasons for this are detailed below. \todo{Ref} + We will use the normal Core representation, not the simplified Core. Even + though the simplified Core version is an equivalent, but simpler + definition, some problems were encountered with it in practice. The + simplifier restructures some (stateful) functions in a way the normalizer + and the \VHDL\ generation cannot handle, leading to uncompilable programs + (whereas the non-simplified version more closely resembles the original + program, allowing the original to be written in a way that can be + handled). This problem is further discussed in + \in{section}[sec:normalization:stateproblems]. The final prototype roughly consists of three steps: @@ -264,7 +308,7 @@ \defref{entry function}Translation of a hardware description always starts at a single function, which is referred to as the \emph{entry - function}. \VHDL is generated for this function first, followed by + function}. \VHDL\ is generated for this function first, followed by any functions used by the entry functions (recursively). \section[sec:prototype:core]{The Core language} @@ -505,7 +549,7 @@ evaluates to this bit. If none of the alternatives match, the \lam{DEFAULT} alternative - is chosen. A case expression must always be exhaustive, \ie it + is chosen. A case expression must always be exhaustive, \ie\ it must cover all possible constructors that the scrutinee can have (if all of them are covered explicitly, the \lam{DEFAULT} alternative can be left out). @@ -524,11 +568,11 @@ f (case a of arg DEFAULT -> arg) \stoplambda - According to the \GHC documentation, this is the only use for the extra + According to the \GHC\ documentation, this is the only use for the extra binder to which the scrutinee is bound. When not using strictness annotations (which is rather pointless in hardware descriptions), \small{GHC} seems to never generate any code making use of this binder. - In fact, \GHC has never been observed to generate code using this + In fact, \GHC\ has never been observed to generate code using this binder, even when strictness was involved. Nonetheless, the prototype handles this binder as expected. @@ -561,7 +605,7 @@ equivalent type. Note that this is not meant to do any actual work, like conversion of data from one format to another, or force a complete type change. Instead, it is meant to change between different representations - of the same type, \eg switch between types that are provably equal (but + of the same type, \eg\ switch between types that are provably equal (but look different). In our hardware descriptions, we typically see casts to change between a @@ -644,7 +688,7 @@ In Core, every expression is typed. The translation to Core happens after the typechecker, so types in Core are always correct as well (though you could of course construct invalidly typed expressions - through the \GHC API). + through the \GHC\ API). Any type in core is one of the following: @@ -755,7 +799,7 @@ Without going into the implementation details, a dictionary can be seen as a lookup table all the methods for a given (single) type class instance. This means that all the dictionaries for the same type class - look the same (\eg contain methods with the same names). However, + look the same (\eg\ contain methods with the same names). However, dictionaries for different instances of the same class contain different methods, of course. @@ -832,7 +876,7 @@ Word} and \hs{Word} types by pattern matching and by using the explicit the \hs{State constructor}. - This explicit conversion makes the \VHDL generation easier: Whenever we + This explicit conversion makes the \VHDL\ generation easier: Whenever we remove (unpack) the \hs{State} type, this means we are accessing the current state (\eg, accessing the register output). Whenever we are a adding (packing) the \hs{State} type, we are producing a new value for @@ -856,7 +900,7 @@ \subsubsection{Different input and output types} An alternative could be to use different types for input and output - state (\ie current and updated state). The accumulator example would + state (\ie\ current and updated state). The accumulator example would then become something like: \starthaskell @@ -946,7 +990,7 @@ Now its clear how to put state annotations in the Haskell source, there is the question of how to implement this state translation. As we have seen in \in{section}[sec:prototype:design], the translation to - \VHDL happens as a simple, final step in the compilation process. + \VHDL\ happens as a simple, final step in the compilation process. This step works on a core expression in normal form. The specifics of normal form will be explained in \in{chapter}[chap:normalization], but the examples given should be @@ -989,7 +1033,7 @@ Before describing how to translate state from normal form to \VHDL, we will first see how state handling looks in normal form. What limitations are there on their use to guarantee that proper - \VHDL can be generated? + \VHDL\ can be generated? We will try to formulate a number of rules about what operations are allowed with state variables. These rules apply to the normalized Core @@ -1138,11 +1182,11 @@ The prototype currently does not check much of the above conditions. This means that if the conditions are violated, sometimes a compile error is generated, but in other cases output - can be generated that is not valid \VHDL or at the very least does + can be generated that is not valid \VHDL\ or at the very least does not correspond to the input. \subsection{Translating to \VHDL} - As noted above, the basic approach when generating \VHDL for stateful + As noted above, the basic approach when generating \VHDL\ for stateful functions is to generate a single register for every stateful function. We look around the normal form to find the let binding that removes the \lam{State} newtype (using a cast). We also find the let binding that @@ -1154,12 +1198,12 @@ This approach seems simple enough, but will this also work for more complex stateful functions involving substates? Observe that any - component of a function's state that is a substate, \ie passed on as + component of a function's state that is a substate, \ie\ passed on as the state of another function, should have no influence on the hardware generated for the calling function. Any state-specific \small{VHDL} for this component can be generated entirely within the called function. So, we can completely ignore substates when - generating \VHDL for a function. + generating \VHDL\ for a function. From this observation it might seem logical to remove the substates from a function's states altogether and leave only the @@ -1190,12 +1234,12 @@ to \lam{s'}. However, \lam{s'} is build up from both \lam{accs'} and \lam{count'}, while only \lam{count'} should end up in the register. \lam{accs'} is a substate for the \lam{acc} function, for which a - register will be created when generating \VHDL for the \lam{acc} + register will be created when generating \VHDL\ for the \lam{acc} function. Fortunately, the \lam{accs'} variable (and any other substate) has a property that we can easily check: It has a \lam{State} type - annotation. This means that whenever \VHDL is generated for a tuple + annotation. This means that whenever \VHDL\ is generated for a tuple (or other algebraic type), we can simply leave out all elements that have a \lam{State} type. This will leave just the parts of the state that do not have a \lam{State} type themselves, like \lam{count'}, @@ -1229,7 +1273,7 @@ When applying these rules to the description in \in{example}[ex:AvgStateNormal], we be left with the description in \in{example}[ex:AvgStateRemoved]. All the parts that do not - generate any \VHDL directly are crossed out, leaving just the + generate any \VHDL\ directly are crossed out, leaving just the actual flow of values in the final hardware. \startlambda @@ -1262,7 +1306,7 @@ removed, leaving us just with the state of \lam{avg} itself. As an illustration of the result of this function, - \in{example}[ex:AccStateVHDL] and \in{example}[ex:AvgStateVHDL] show the the \VHDL that is + \in{example}[ex:AccStateVHDL] and \in{example}[ex:AvgStateVHDL] show the the \VHDL\ that is generated from the examples is this section. \startbuffer[AvgStateVHDL] @@ -1340,9 +1384,9 @@ end architecture structural; \stopbuffer - \placeexample[][ex:AccStateVHDL]{\VHDL generated for acc from \in{example}[ex:AvgState]} + \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for acc from \in{example}[ex:AvgState]} {\typebuffer[AccStateVHDL]} - \placeexample[][ex:AvgStateVHDL]{\VHDL generated for avg from \in{example}[ex:AvgState]} + \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for avg from \in{example}[ex:AvgState]} {\typebuffer[AvgStateVHDL]} % \subsection{Initial state} % How to specify the initial state? Cannot be done inside a hardware @@ -1356,6 +1400,5 @@ % Implementation issues: state splitting, linking input to output state, % checking usage constraints on state variables. % -% \todo{Implementation issues: Separate compilation, simplified core.} % % vim: set sw=2 sts=2 expandtab: