X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FPrototype.tex;h=293e00451a76c0647b8d58c480e7b7cd1aca9c75;hp=945e920c33a5956bb611a1eb69635124fa6b19d0;hb=77f079684a01c329d10d1cd00cf5e4ee1d05377f;hpb=fc1688977fdd8ee18e027876b8d86b0c38e25540 diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex index 945e920..293e004 100644 --- a/Chapters/Prototype.tex +++ b/Chapters/Prototype.tex @@ -1,4 +1,4 @@ -\chapter{Prototype} +\chapter[chap:prototype]{Prototype} An important step in this research is the creation of a prototype compiler. Having this prototype allows us to apply the ideas from the previous chapter to actual hardware descriptions and evaluate their usefulness. Having a @@ -149,7 +149,7 @@ newEmptyBox.inp(0,0); newBox.front(btex \small{GHC} frontend + desugarer etex); newBox.norm(btex Normalization etex); - newBox.vhdl(btex VHDL generation etex); + newBox.vhdl(btex \small{VHDL} generation etex); newEmptyBox.out(0,0); % Space the boxes evenly @@ -166,7 +166,7 @@ ObjLabel.inp(btex Haskell source etex) "labpathname(haskell)", "labdir(rt)"; ObjLabel.front(btex Core etex) "labpathname(core)", "labdir(rt)"; ObjLabel.norm(btex Normalized core etex) "labpathname(normal)", "labdir(rt)"; - ObjLabel.vhdl(btex VHDL description etex) "labpathname(vhdl)", "labdir(rt)"; + ObjLabel.vhdl(btex \small{VHDL} description etex) "labpathname(vhdl)", "labdir(rt)"; % Draw the objects (and deferred labels) drawObj (inp, front, norm, vhdl, out); @@ -185,9 +185,9 @@ order expressions, has a specific structure, etc.), but is also very close to directly describing hardware. \stopdesc - \startdesc{VHDL generation} + \startdesc{\small{VHDL} generation} The last step takes the normal formed core representation and generates - VHDL for it. Since the normal form has a specific, hardware-like + \small{VHDL} for it. Since the normal form has a specific, hardware-like structure, this final step is very straightforward. \stopdesc