X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FNormalization.tex;h=71e71eb33ae78160d51b1fa9981847d233d3fd58;hp=f64f7909aab0fbedf59e4d5c5a0c7d2777a5f927;hb=77f079684a01c329d10d1cd00cf5e4ee1d05377f;hpb=21c8a86147c874c29156d1859a670c3f7c6df7ee

diff --git a/Chapters/Normalization.tex b/Chapters/Normalization.tex
index f64f790..71e71eb 100644
--- a/Chapters/Normalization.tex
+++ b/Chapters/Normalization.tex
@@ -35,15 +35,15 @@
 %%  \stopcombination
 %}
 
-The first step in the core to VHDL translation process, is normalization. We
+The first step in the core to \small{VHDL} translation process, is normalization. We
 aim to bring the core description into a simpler form, which we can
-subsequently translate into VHDL easily. This normal form is needed because
-the full core language is more expressive than VHDL in some areas and because
+subsequently translate into \small{VHDL} easily. This normal form is needed because
+the full core language is more expressive than \small{VHDL} in some areas and because
 core can describe expressions that do not have a direct hardware
 interpretation.
 
-TODO: Describe core properties not supported in VHDL, and describe how the
-VHDL we want to generate should look like.
+TODO: Describe core properties not supported in \small{VHDL}, and describe how the
+\small{VHDL} we want to generate should look like.
 
 \section{Normal form}
 The transformations described here have a well-defined goal: To bring the
@@ -73,10 +73,10 @@ describing the things we want to not have in a normal form.
   generate a hardware signal that contains a function, so all values,
   arguments and returns values used must be first order.
 
-  \item Any complex \emph{nested scopes} must be removed. In the VHDL
+  \item Any complex \emph{nested scopes} must be removed. In the \small{VHDL}
   description, every signal is in a single scope. Also, full expressions are
   not supported everywhere (in particular port maps can only map signal names,
-  not expressions). To make the VHDL generation easy, all values must be bound
+  not expressions). To make the \small{VHDL} generation easy, all values must be bound
   on the \quote{top level}.
 \stopitemize
 
@@ -364,7 +364,7 @@ the output port. Most function applications bound by the let expression
 define a component instantiation, where the input and output ports are mapped
 to local signals or arguments. Some of the others use a builtin
 construction (\eg the \lam{case} statement) or call a builtin function
-(\eg \lam{add} or \lam{sub}). For these, a hardcoded VHDL translation is
+(\eg \lam{add} or \lam{sub}). For these, a hardcoded \small{VHDL} translation is
 available.
 
 \subsection{Definitions}
@@ -629,7 +629,7 @@ M
 This transformation inlines simple let bindings (\eg a = b).
 
 This transformation is not needed to get into normal form, but makes the
-resulting VHDL a lot shorter.
+resulting \small{VHDL} a lot shorter.
 
 \starttrans
 letnonrec
@@ -663,7 +663,7 @@ This normalization pass should really be unneeded to get into normal form
 (since ununsed bindings are not forbidden by the normal form), but in practice
 the desugarer or simplifier emits some unused bindings that cannot be
 normalized (e.g., calls to a \type{PatError} (TODO: Check this name)). Also,
-this transformation makes the resulting VHDL a lot shorter.
+this transformation makes the resulting \small{VHDL} a lot shorter.
 
 \starttrans
 let a = E in M
@@ -910,7 +910,7 @@ divide them into two categories:
         
         These arguments cannot be preserved in the program, since we
         cannot represent them as input or output ports in the resulting
-        VHDL. To remove them, we create a specialized version of the
+        \small{VHDL}. To remove them, we create a specialized version of the
         called function with these arguments filled in. This is done by
         the argument propagation transform.
 
@@ -1015,7 +1015,7 @@ into categories:
 \subsubsection{Argument simplification}
 This transform deals with arguments to functions that
 are of a runtime representable type. It ensures that they will all become
-references to global variables, or local signals in the resulting VHDL. 
+references to global variables, or local signals in the resulting \small{VHDL}. 
 
 TODO: It seems we can map an expression to a port, not only a signal.
 Perhaps this makes this transformation not needed?
@@ -1056,7 +1056,7 @@ the original argument.
 
 This transformation is useful when applying higher order builtin functions
 like \hs{map} to a lambda abstraction, for example. In this case, the code
-that generates VHDL for \hs{map} only needs to handle top level functions and
+that generates \small{VHDL} for \hs{map} only needs to handle top level functions and
 partial applications, not any other expression (such as lambda abstractions or
 even more complicated expressions).