X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FNormalization.tex;h=2d82716401854391475606611d4068569ad7177a;hp=89c2d4a13faafd1ac6df231082632d1d78777148;hb=05ad754047f8965ea7d330d1b4a09ff53ce7f09d;hpb=42ec9c78da464de1ed58509a6edaa454c6a225bc

diff --git a/Chapters/Normalization.tex b/Chapters/Normalization.tex
index 89c2d4a..2d82716 100644
--- a/Chapters/Normalization.tex
+++ b/Chapters/Normalization.tex
@@ -901,11 +901,11 @@
         architecture which would just add its inputs. This generates a lot of
         overhead in the VHDL, which is particularly annoying when browsing the
         generated RTL schematic (especially since + is not allowed in VHDL
-        architecture names\footnote{Technically, it is allowed when using
-        extended identifiers, but it seems that none of the tooling likes
-        extended identifiers in filenames, so it effectively doesn't work}, so
-        the entity would be called \quote{w7aA7f} or something similarly
-        unreadable and autogenerated).
+        architecture names\footnote{Technically, it is allowed to use
+        non-alphanumerics when using extended identifiers, but it seems that
+        none of the tooling likes extended identifiers in filenames, so it
+        effectively doesn't work}, so the entity would be called
+        \quote{w7aA7f} or something similarly unreadable and autogenerated).
 
     \subsection{Program structure}
       These transformations are aimed at normalizing the overall structure