X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FIntroduction.tex;h=3b0a5c1ec9c2723f0968ea0956766d563389f958;hp=334b1c89d734486f1f960bb92717f767b43c5a8c;hb=10aead726acc0c5a8a17d76f10e6fd1aa0c94319;hpb=7d47b9a2f541f9e16a70599f8b76bd14bd862d20

diff --git a/Chapters/Introduction.tex b/Chapters/Introduction.tex
index 334b1c8..3b0a5c1 100644
--- a/Chapters/Introduction.tex
+++ b/Chapters/Introduction.tex
@@ -65,7 +65,7 @@ advanced types and provides a case study.
     % Draw a dotted line between the middle operations
     ncline(a2)(a3) "linestyle(dashed withdots)", "arrows(-)";
   \stopuseMPgraphic
-  \placeexample[here][ex:AndWord]{Simple architecture that inverts a vector of bits.}
+  \placeexample[][ex:AndWord]{Simple architecture that inverts a vector of bits.}
     \startcombination[2*1]
       {\typebufferlam{AndWord}}{Haskell description of the architecture.}
       {\boxedgraphic{AndWord}}{The architecture described by the Haskell description.}
@@ -220,7 +220,7 @@ advanced types and provides a case study.
   In addition to looking at designing a hardware description language, we
   will also implement a prototype to test ideas. This prototype will
   translate hardware descriptions written in the Haskell functional language
-  to simple (netlist-like) hardware descriptions in the \VHDL language. The
+  to simple (netlist-like) hardware descriptions in the \VHDL\ language. The
   reasons for choosing these languages are detailed in section
   \in{}[sec:prototype:input] and \in{}[sec:prototype:output] respectively.