X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Freport.git;a=blobdiff_plain;f=Chapters%2FHardwareDescription.tex;h=ff4b0c0b3143c78983f6464ad52d95e090b5488f;hp=d90a2e1b6d5e1d891b740225f4807c50d317845c;hb=d92aa4307ca45f07c6ae50056e08ffc874839756;hpb=f07d21119a95b40eb7f4bed07356e3963007f3f3 diff --git a/Chapters/HardwareDescription.tex b/Chapters/HardwareDescription.tex index d90a2e1..ff4b0c0 100644 --- a/Chapters/HardwareDescription.tex +++ b/Chapters/HardwareDescription.tex @@ -56,7 +56,6 @@ \section[sec:description:application]{Function application} - \todo{Sidenote: Inputs vs arguments} The basic syntactic elements of a functional program are functions and function application. These have a single obvious \small{VHDL} translation: Each top level function becomes a hardware component, where each @@ -70,9 +69,9 @@ mapped to a signal, which is used as the result of the application. Since every top level function generates its own component, the - hierarchy of of function calls is reflected in the final \VHDL output - as well, creating a hierarchical \VHDL description of the hardware. - This separation in different components makes the resulting \VHDL + hierarchy of of function calls is reflected in the final \VHDL\ output + as well, creating a hierarchical \VHDL\ description of the hardware. + This separation in different components makes the resulting \VHDL\ output easier to read and debug. \in{Example}[ex:And3] shows a simple program using only function @@ -136,8 +135,7 @@ and3 a b c = and (and a b) c the condition is false. This \hs{if} function would then essentially describe a multiplexer and - allows us to describe any architecture that uses multiplexers. \fxnote{Are - there other mechanisms of choice in hardware?} + allows us to describe any architecture that uses multiplexers. However, to be able to describe our hardware in a more convenient way, we also want to translate Haskell's choice mechanisms. The easiest of these @@ -146,7 +144,26 @@ and3 a b c = and (and a b) c simply be translated to a conditional assignment, where the conditions use equality comparisons against the constructors in the \hs{case} expressions. - \todo{Assignment vs multiplexers} + \placeintermezzo{}{ + \defref{substitution notation} + \startframedtext[width=8cm,background=box,frame=no] + \startalignment[center] + {\tfa Arguments / results vs. inputs / outputs} + \stopalignment + \blank[medium] + Due to the translation chosen for function application, there is a + very strong relation between arguments, results, inputs and outputs. + For clarity, the former two will always refer to the arguments and + results in the functional description (either Haskell or Core). The + latter two will refer to input and output ports in the generated + \VHDL. + + Even though these concepts seem to be nearly identical, when stateful + functions are introduces we will see arguments and results that will + not get translated into input and output ports, making this + distinction more important. + \stopframedtext + } In \in{example}[ex:CaseInv] a simple \hs{case} expression is shown, scrutinizing a boolean value. The corresponding architecture has a @@ -160,11 +177,9 @@ and3 a b c = and (and a b) c the comparator and directly feed 'in' into the multiplexer (or even use an inverter instead of a multiplexer). However, we will try to make a general translation, which works for all possible \hs{case} expressions. - Optimizations such as these are left for the \VHDL synthesizer, which + Optimizations such as these are left for the \VHDL\ synthesizer, which handles them very well. - \todo{Be more explicit about >2 alternatives} - \startbuffer[CaseInv] inv :: Bool -> Bool inv x = case x of @@ -235,6 +250,11 @@ and3 a b c = and (and a b) c nested) multiplexers. These multiplexers are driven by comparators and other logic, that check each pattern in turn. + In these examples we have seen only binary case expressions and pattern + matches (\ie, with two alternatives). In practice, case expressions can + choose between more than two values, resulting in a number of nested + multiplexers. + \section{Types} Translation of two most basic functional concepts has been discussed: Function application and choice. Before looking further @@ -342,7 +362,7 @@ and3 a b c = and (and a b) c Here, a type synonym \hs{RegisterIndex} is defined that is equal to the \hs{RangedWord} type constructor applied to the type \hs{D7}. In other words, this defines an unsigned word with values from - \lam{0} to \lam{7} (inclusive). This word can be be used to index the + {\definedfont[Serif*normalnum]0 to 7} (inclusive). This word can be be used to index the 8 element vector \hs{RegisterState} above. This type is translated to the \type{unsigned} \small{VHDL} type. @@ -354,17 +374,17 @@ and3 a b c = and (and a b) c \subsection{User-defined types} There are three ways to define new types in Haskell: Algebraic datatypes with the \hs{data} keyword, type synonyms with the \hs{type} - keyword and type renamings with the \hs{newtype} keyword. \GHC + keyword and type renamings with the \hs{newtype} keyword. \GHC\ offers a few more advanced ways to introduce types (type families, existential typing, \small{GADT}s, etc.) which are not standard Haskell. These will be left outside the scope of this research. Only an algebraic datatype declaration actually introduces a - completely new type, for which we provide the \VHDL translation + completely new type, for which we provide the \VHDL\ translation below. Type synonyms and renamings only define new names for existing types (where synonyms are completely interchangeable and renamings need explicit conversion). Therefore, these do not need - any particular \VHDL translation, a synonym or renamed type will + any particular \VHDL\ translation, a synonym or renamed type will just use the same representation as the original type. The distinction between a renaming and a synonym does no longer matter in hardware and can be disregarded in the generated \VHDL. @@ -382,7 +402,7 @@ and3 a b c = and (and a b) c to this type. The collection for a product type is the Cartesian product of the collections for the types of its fields. - These types are translated to \VHDL record types, with one field for + These types are translated to \VHDL\ record types, with one field for every field in the constructor. This translation applies to all single constructor algebraic datatypes, including those with just one field (which are technically not a product, but generate a VHDL @@ -397,7 +417,7 @@ and3 a b c = and (and a b) c Note that Haskell's \hs{Bool} type is also defined as an enumeration type, but we have a fixed translation for that. - These types are translated to \VHDL enumerations, with one value for + These types are translated to \VHDL\ enumerations, with one value for each constructor. This allows references to these constructors to be translated to the corresponding enumeration value. \stopdesc @@ -413,7 +433,7 @@ and3 a b c = and (and a b) c union of the the collections for each of the constructors. Sum types are currently not supported by the prototype, since there is - no obvious \VHDL alternative. They can easily be emulated, however, as + no obvious \VHDL\ alternative. They can easily be emulated, however, as we will see from an example: \starthaskell @@ -436,7 +456,7 @@ and3 a b c = and (and a b) c last one if \hs{B}), all the other ones have no useful value. An obvious problem with this naive approach is the space usage: The - example above generates a fairly big \VHDL type. Since we can be + example above generates a fairly big \VHDL\ type. Since we can be sure that the two \hs{Word}s in the \hs{Sum} type will never be valid at the same time, this is a waste of space. @@ -466,13 +486,13 @@ and3 a b c = and (and a b) c If the naive approach for sum types described above would be used, a record would be created where the first field is an enumeration to distinguish \hs{Empty} from \hs{Cons}. Furthermore, two more - fields would be added: One with the (\VHDL equivalent of) type + fields would be added: One with the (\VHDL\ equivalent of) type \hs{t} (assuming this type is actually known at compile time, this should not be a problem) and a second one with type \hs{List t}. The latter one is of course a problem: This is exactly the type that was to be translated in the first place. - The resulting \VHDL type will thus become infinitely deep. In + The resulting \VHDL\ type will thus become infinitely deep. In other words, there is no way to statically determine how long (deep) the list will be (it could even be infinite). @@ -665,7 +685,7 @@ quadruple n = mul (mul n) Fortunately, we can again use the principle of specialization: Since every function application generates a separate piece of hardware, we can know the types of all arguments exactly. Provided that existential typing - (which is a \GHC extension) is not used typing, all of the + (which is a \GHC\ extension) is not used typing, all of the polymorphic types in a function must depend on the types of the arguments (In other words, the only way to introduce a type variable is in a lambda abstraction). @@ -990,7 +1010,7 @@ acc in s = (s', out) result is stateful. This means that the annotation lives \quote{outside} of the function, it is completely invisible when looking at the function body. - \item Use some kind of annotation on the type level, \ie give stateful + \item Use some kind of annotation on the type level, \ie\ give stateful arguments and stateful (parts of) results a different type. This has the potential to make this annotation visible inside the function as well, such that when looking at a value inside the function body you can @@ -1101,7 +1121,7 @@ acc in s = (s', out) (evaluation of constant comparisons), to ensure non-termination. Supporting general recursion will probably require strict conditions on the input descriptions. Even then, it will be hard (if not - impossible) to really guarantee termination, since the user (or \GHC + impossible) to really guarantee termination, since the user (or \GHC\ desugarer) might use some obscure notation that results in a corner case of the simplifier that is not caught and thus non-termination.