Put a VHDL in smallcaps.

[matthijs/master-project/report.git] / Chapters / Normalization.tex

diff --git a/Chapters/Normalization.tex b/Chapters/Normalization.tex
index 4e0075946eb3475e06f81076aec02d69c5a07de9..ca84ed171760e6af2a40cf3f418025a4d13c15bc 100644 (file)
--- a/Chapters/Normalization.tex
+++ b/Chapters/Normalization.tex
@@ -952,10 +952,10 @@
 
         \transexample{toplevelinline}{Top level binding inlining}{from}{to}
        
-        Example \in{ex:trans:toplevelinline} shows a typical application of
+        \in{Example}[ex:trans:toplevelinline] shows a typical application of
         the addition operator generated by \GHC. The type and dictionary
         arguments used here are described in
-        \in{section:prototype:polymorphism}.
+        \in{Section}[section:prototype:polymorphism].
 
         Without this transformation, there would be a (+) entity in the
         architecture which would just add its inputs. This generates a lot of