Add section on EDSLs.

[matthijs/master-project/report.git] / Chapters / Future.tex

diff --git a/Chapters/Future.tex b/Chapters/Future.tex
index 852d14fe179308df40ffed123e3b5979d674ced9..9c60dfe8e3b8f656ef0bd8a74e67fa6a98b4e80b 100644 (file)
--- a/Chapters/Future.tex
+++ b/Chapters/Future.tex
@@ -391,8 +391,8 @@ behaviour is not needed.
 
 The main cost of this approach will probably be extra complexity in the
 compiler: The paths (state) data can take become very non-trivial, and it
-is probably hard to properly analyze these paths and produce the intended VHDL
-description.
+is probably hard to properly analyze these paths and produce the
+intended \VHDL description.
 
 \section{Multiple cycle descriptions}
 In the current Cλash prototype, every description is a single-cycle