Implementation issues State Prototype Stages (-> Core, Normalization, -> VHDL) Core VHDL vs EDIF generation Normalization Normal form Rules used Completeness / conditions on input Termination Casts Context Other FHDLs VHDL / Verilog / EDIF etc. Advantages of clash / why clash? Haskell as hardware Dependent types Impossible things: Infinite recursion, higher order expressions Haskell language coverage / constraints Recursion Builtin types Custom types (Sum types, product types) Function types / higher order expressions Future work Boilerplate reduction (State distribution & pipelining) Recursion Multiple time domains Multiple cycle descriptions