From: Matthijs Kooijman Date: Mon, 31 Aug 2009 12:35:03 +0000 (+0200) Subject: Improve presentation, based on comments. X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=commitdiff_plain;h=f8ca52f68083c6d4081b509681c24b6e059a9eb3 Improve presentation, based on comments. Changes are untested, since things wouldn't compile here. --- diff --git a/PolyAlu.lhs b/PolyAlu.lhs index 5ff0a60..547f095 100644 --- a/PolyAlu.lhs +++ b/PolyAlu.lhs @@ -13,9 +13,9 @@ import qualified Prelude as P \frame { \frametitle{Small Use Case}\pause +TODO: Plaatje \begin{itemize} - \item Small Polymorphic, Higher-Order CPU\pause - \item Each function is turned into a hardware component\pause + \item Polymorphic, Higher-Order CPU\pause \item Use of state will be simple \end{itemize} }\note[itemize]{ @@ -25,36 +25,15 @@ import qualified Prelude as P \item Use of state will be kept simple } -\frame -{ -\frametitle{Imports}\pause -Import all the built-in types, such as vectors and integers: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -\begin{code} -import CLasH.HardwareTypes -\end{code} -\end{beamercolorbox}\pause - -Import annotations, helps \clash{} to find top-level component: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -\begin{code} -import CLasH.Translator.Annotations -\end{code} -\end{beamercolorbox} -}\note[itemize]{ -\item The first input is always needed, as it contains the builtin types -\item The second one is only needed if you want to make use of Annotations -} - \subsection{Type Definitions} \frame { \frametitle{Type definitions}\pause +TODO: Plaatje van de ALU First we define some ALU types: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -type Op s a = a -> Vector s a -> a -type Opcode = Bit +type Op a = a -> a -> a \end{code} \end{beamercolorbox}\pause @@ -65,58 +44,22 @@ type RegBank s a = Vector (s :+: D1) a type RegState s a = State (RegBank s a) \end{code} \end{beamercolorbox}\pause - -And a simple Word type: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -\begin{code} -type Word = SizedInt D12 -\end{code} -\end{beamercolorbox} }\note[itemize]{ -\item The first type is already polymorphic, both in size, and element type -\item It's a small example, so Opcode is just a Bit +\item The first type is already polymorphic in input / output type \item State has to be of the State type to be recognized as such -\item SizedInt D12: One concrete type for now, to make the signatures smaller -} - -\subsection{Frameworks for Operations} -\frame -{ -\frametitle{Operations}\pause -We make a primitive operation: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -\begin{code} -primOp :: {-"{\color<4>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a -primOp f a b = a `f` a -\end{code} -\end{beamercolorbox}\pause - -We make a vector operation: -\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} -\begin{code} -vectOp :: {-"{\color<4>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a -vectOp f a b = {-"{\color<4>[rgb]{1,0,0}"-}foldl{-"}"-} f a b -\end{code} -\end{beamercolorbox} -\begin{itemize} -\uncover<4->{\item We support Higher-Order Functionality} -\end{itemize} -}\note[itemize]{ -\item These are just frameworks for 'real' operations -\item Notice how they are High-Order functions } \subsection{Polymorphic, Higher-Order ALU} \frame { \frametitle{Simple ALU} -We define a polymorphic ALU: +Abstract ALU definition: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} +type Opcode = Bit alu :: - Op s a -> - Op s a -> - Opcode -> a -> Vector s a -> a + Op a -> Op a -> + Opcode -> a -> a -> a alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-} a b = op1 a b alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \end{code} @@ -126,6 +69,7 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \end{itemize} }\note[itemize]{ \item Alu is both higher-order, and polymorphic +\item Two parameters are "compile time", others are "runtime" \item We support pattern matching } @@ -135,17 +79,17 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \frametitle{Register Bank} Make a simple register bank: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} +TODO: Hide type sig \begin{code} registerBank :: - CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s -> - RangedWord s -> Bit -> ((RegState s a), a ) + CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s -> + RangedWord s -> Bool -> (RegState s a) -> ((RegState s a), a ) -registerBank (State mem) data_in rdaddr wraddr wrenable = +registerBank data_in rdaddr wraddr (State mem) = ((State mem'), data_out) where - data_out = mem!rdaddr - mem' {-"{\color<2>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-} = mem - {-"{\color<2>[rgb]{1,0,0}"-}| otherwise{-"}"-} = replace mem wraddr data_in + data_out = mem!rdaddr + mem' = replace mem wraddr data_in \end{code} \end{beamercolorbox} \begin{itemize} @@ -155,6 +99,7 @@ registerBank (State mem) data_in rdaddr wraddr wrenable = \item RangedWord runs from 0 to the upper bound \item mem is statefull \item We support guards +\item replace is a builtin function } \subsection{Simple CPU: ALU \& Register Bank} @@ -163,24 +108,24 @@ registerBank (State mem) data_in rdaddr wraddr wrenable = \frametitle{Simple CPU} Combining ALU and register bank: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} +TODO: Hide Instruction type? \begin{code} +type Instruction = (Opcode, Word, RangedWord D9, RangedWord D9) -> RegState D9 Word -> {-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-} actual_cpu :: - (Opcode, Word, Vector D4 Word, RangedWord D9, - RangedWord D9, Bit) -> RegState D9 Word -> - (RegState D9 Word, Word) + Instruction -> RegState D9 Word -> (RegState D9 Word, Word) -actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out) +actual_cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out) where - alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}primOp (+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}vectOp (+){-"}"-}) opc ram_out b - (ram',ram_out) = registerBank ram a rdaddr wraddr wren + alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}(+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}(-){-"}"-}) opc d ram_out + (ram',ram_out) = registerBank alu_out rdaddr wraddr ram \end{code} \end{beamercolorbox} \begin{itemize} \uncover<2->{\item Annotation is used to indicate top-level component} \end{itemize} }\note[itemize]{ -\item We use the new Annotion functionality to indicate this is the top level +\item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us. \item the primOp and vectOp frameworks are now supplied with real functionality, the plus (+) operations \item No polymorphism or higher-order stuff is allowed at this level. \item Functions must be specialized, and have primitives for input and output @@ -214,4 +159,4 @@ main = do mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output return () \end{code} -%endif \ No newline at end of file +%endif diff --git a/clash-haskell09.lhs b/clash-haskell09.lhs index 8975cfd..3f28819 100644 --- a/clash-haskell09.lhs +++ b/clash-haskell09.lhs @@ -6,6 +6,7 @@ \title{\clash{}} \subtitle{From Haskell To Hardware} \author{Christiaan Baaij \& Matthijs Kooijman} +\author{Supervisor: Jan Kuper} \date{September 3, 2009} \begin{document} diff --git a/clash-haskell09.pdf b/clash-haskell09.pdf deleted file mode 100644 index 56da49e..0000000 Binary files a/clash-haskell09.pdf and /dev/null differ diff --git a/demo.lhs b/demo.lhs index e4f8d48..0399cc8 100644 --- a/demo.lhs +++ b/demo.lhs @@ -3,11 +3,13 @@ \frame{ \frametitle{Demo} \begin{itemize} - \item We will simulate the small CPU from earlier + \item We will simulate the small CPU \item Translate that CPU code to VHDL \item Simulate the generated VHDL \item See the hardware schematic of the synthesized VHDL \end{itemize} +}\note[itemize]{ +\item Will show video } % diff --git a/howdoesitwork.lhs b/howdoesitwork.lhs index 342be54..b9970d6 100644 --- a/howdoesitwork.lhs +++ b/howdoesitwork.lhs @@ -8,13 +8,13 @@ \item No Effort:\\ GHC API Parses, Typechecks and Desugars the Haskell code \pause \item Hard: \\ - Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form \pause + Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form. Uses reduction rules. \pause \item Easy: \\ Translate Normalized Core to synthesizable VHDL \end{itemize} }\note[itemize]{ \item Here is a quick insight as to how WE translate Haskell to Hardware -\item You can also use TH, like ForSyDe. Or traverse datastructures, like +\item Normal form already looks like hardware (components and lines) +\item You can also use TH, like ForSyDe. Or traverse datastructures, like ? \item We're in luck with the GHC API update of 6.10 and onwards -\item Normal form is a single lamda and a let expression, every let binder is a simple assignment -} \ No newline at end of file +} diff --git a/introduction.lhs b/introduction.lhs index 1066173..e0a72ff 100644 --- a/introduction.lhs +++ b/introduction.lhs @@ -5,15 +5,15 @@ { \frametitle{What is \clash{}?}\pause \begin{itemize} - \item \clash{}: CAES Language for Hardware Descriptions\pause + \item \clash{}: CAES Language for Hardware\pause \item Rapid prototyping language\pause \item Subset of Haskell can be translated to Hardware (VHDL)\pause - \item Structural Description of a Mealy Machine + \item Structural Description of the logic part of a Mealy Machine \end{itemize} } \note[itemize] { -\item We are a Computer Architectures group, this has been a 6 month project, no prior experience with Haskell. +\item We are a Computer Architectures group, this has been a Masters' project, no prior experience with Haskell. \item \clash{} is written in Haskell, of course \item \clash{} is currently meant for rapid prototyping, not verification of hardware desigs \item Functional languages are close to Hardware @@ -24,7 +24,7 @@ \subsection{Mealy Machine} \frame { -\frametitle{What again is a Mealy Machine?} +\frametitle{What is a Mealy Machine again?} \begin{figure} \centerline{\includegraphics[width=10cm]{mealymachine}} \label{img:mealymachine} @@ -32,6 +32,10 @@ } \note[itemize]{ \item Mealy machine bases its output on current input and previous state +\item: TODO: Integrate this slide with the next two. First, show the picture +with the mealyMachine type signature (and rename it to "func"). Then, show the +run function, without type signature. Focus is on correspondence to the +picture. } \frame @@ -43,10 +47,6 @@ mealyMachine :: InputSignals -> {-"{\color<2>[rgb]{1,0,0}"-}State{-"}"-} -> (State, OutputSignals) -mealyMachine inputs {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-}, output) - where - {-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-} = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input - outputs = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input \end{code} \end{beamercolorbox} \begin{itemize} @@ -74,6 +74,7 @@ run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out \end{beamercolorbox} \begin{itemize} \item State behaves like an accumulator +\item Input is a (normal) list of inputs, one for each cycle \end{itemize} } \note[itemize]{ diff --git a/reducer.lhs b/reducer.lhs index cc6d89f..4d74c68 100644 --- a/reducer.lhs +++ b/reducer.lhs @@ -2,27 +2,22 @@ \frame{ \frametitle{More than just toys} \pause +TODO: Plaatje van de reducer \begin{itemize} - \item We designed a reduction circuit in \clash{}\pause + \item We implemented a reduction circuit in \clash{}\pause \item Simulation results in Haskell match VHDL simulation results\pause \item Synthesis completes without errors or warnings\pause - \item For the same Virtex-4 FPGA: \pause - \begin{itemize} - \item Hand coded VHDL design runs at 200 MHz\pause - \item \clash{} design runs at around 85* MHz - \end{itemize} + \item Around half speed of handcoded and optimized VHDL \pause \end{itemize} -\vspace{6em} -\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}} }\note[itemize]{ \item Toys like the poly cpu one are good to give a quick demo \item But we used \clash{} to design 'real' hardware \item Reduction circuit sums the numbers in a row of a (sparse) matrix -\item Nice speed considering we don't optimize for it +\item Nice speed considering we don't optimize for it (only single example!) } \begin{frame}[plain] \begin{centering} \includegraphics[height=\paperheight]{reducerschematic.png} \end{centering} -\end{frame} \ No newline at end of file +\end{frame}