From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Wed, 26 Aug 2009 21:08:52 +0000 (+0200)
Subject: Complete draft version of the presentation
X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=commitdiff_plain;h=2523b691bc4f9871e5d0fb3823fcd2c8952affaa

Complete draft version of the presentation
---

diff --git a/PolyAlu.hs b/PolyAlu.hs
index 23dfaa4..21f6eff 100644
--- a/PolyAlu.hs
+++ b/PolyAlu.hs
@@ -21,17 +21,16 @@ primOp f a b = a `f` a
 {-# LINE 84 "PolyAlu.lhs" #-}
 vectOp :: (a -> a -> a) -> Op s a
 vectOp f a b = foldl f a b
-{-# LINE 96 "PolyAlu.lhs" #-}
+{-# LINE 99 "PolyAlu.lhs" #-}
 alu :: 
   Op s a -> 
   Op s a -> 
   Opcode -> a -> Vector s a -> a
 alu op1 op2 Low    a b = op1 a b
 alu op1 op2 High   a b = op2 a b
-{-# LINE 112 "PolyAlu.lhs" #-}
+{-# LINE 118 "PolyAlu.lhs" #-}
 registerBank :: 
-  ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
-  (RegState s a) -> a -> RangedWord s ->
+  ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
   RangedWord s -> Bit -> ((RegState s a), a )
   
 registerBank (State mem) data_in rdaddr wraddr wrenable = 
@@ -40,7 +39,7 @@ registerBank (State mem) data_in rdaddr wraddr wrenable =
     data_out  =   mem!rdaddr
     mem'  | wrenable == Low    = mem
           | otherwise          = replace mem wraddr data_in
-{-# LINE 133 "PolyAlu.lhs" #-}
+{-# LINE 141 "PolyAlu.lhs" #-}
 {-# ANN actual_cpu TopEntity#-}
 actual_cpu :: 
   (Opcode, Word, Vector D4 Word, RangedWord D9, 
@@ -51,7 +50,7 @@ actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
   where
     alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
     (ram',ram_out)  = registerBank ram a rdaddr wraddr wren
-{-# LINE 149 "PolyAlu.lhs" #-}
+{-# LINE 160 "PolyAlu.lhs" #-}
 {-# ANN initstate InitState#-}
 initstate :: RegState D9 Word
 initstate = State (copy (0 :: Word))  
diff --git a/PolyAlu.lhs b/PolyAlu.lhs
index 5a4e26a..0d99ca7 100644
--- a/PolyAlu.lhs
+++ b/PolyAlu.lhs
@@ -18,6 +18,11 @@ import qualified Prelude as P
   \item Each function is turned into a hardware component
   \item Use of state will be simple
 \end{itemize}
+}\note[itemize]{
+\item Small "toy"-example of what can be done in \clash{}
+\item Show what can be translated to Hardware
+\item Put your hardware glasses on: each function will be a component
+\item Use of state will be kept simple
 }
 
 \frame
@@ -36,6 +41,9 @@ Import annotations, helps \clash{} to find top-level component:
 import CLasH.Translator.Annotations
 \end{code}
 \end{beamercolorbox}
+}\note[itemize]{
+\item The first input is always needed, as it contains the builtin types
+\item The second one is only needed if you want to make use of Annotations
 }
 
 \subsection{Type Definitions}
@@ -64,6 +72,11 @@ And a simple Word type:
 type Word           =   SizedInt D12
 \end{code}
 \end{beamercolorbox}
+}\note[itemize]{
+\item The first type is already polymorphic, both in size, and element type
+\item It's a small example, so Opcode is just a Bit
+\item State has to be of the State type to be recognized as such
+\item SizedInt D12: One concrete type for now, to make the signatures smaller
 }
 
 \subsection{Frameworks for Operations}
@@ -88,7 +101,11 @@ vectOp f a b = {-"{\color<3>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
 \begin{itemize}
 \uncover<3->{\item We support Higher-Order Functionality}
 \end{itemize}
+}\note[itemize]{
+\item These are just frameworks for 'real' operations
+\item Notice how they are High-Order functions
 }
+
 \subsection{Polymorphic, Higher-Order ALU}
 \frame
 {
@@ -107,7 +124,11 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-}   a b = op2 a b
 \begin{itemize}
 \uncover<2->{\item We support Patter Matching}
 \end{itemize}
+}\note[itemize]{
+\item Alu is both higher-order, and polymorphic
+\item We support pattern matching
 }
+
 \subsection{Register bank}
 \frame
 {
@@ -130,7 +151,12 @@ registerBank (State mem) data_in rdaddr wraddr wrenable =
 \begin{itemize}
 \uncover<2->{\item We support Guards}
 \end{itemize}
+}\note[itemize]{
+\item RangedWord runs from 0 to the upper bound
+\item mem is statefull
+\item We support guards
 }
+
 \subsection{Simple CPU: ALU \& Register Bank}
 \frame
 {
@@ -153,6 +179,11 @@ actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
 \begin{itemize}
 \uncover<2->{\item Annotation is used to indicate top-level component}
 \end{itemize}
+}\note[itemize]{
+\item We use the new Annotion functionality to indicate this is the top level
+\item the primOp and vectOp frameworks are now supplied with real functionality, the plus (+) operations
+\item No polymorphism or higher-order stuff is allowed at this level.
+\item Functions must be specialized, and have primitives for input and output 
 }
 
 %if style == newcode
@@ -180,7 +211,7 @@ main = do
   let input = program
   let istate = initstate
   let output = run actual_cpu istate input
-  mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output
+  mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output
   return ()
 \end{code}
 %endif
\ No newline at end of file
diff --git a/clash-haskell09.lhs b/clash-haskell09.lhs
index c9fac13..445f633 100644
--- a/clash-haskell09.lhs
+++ b/clash-haskell09.lhs
@@ -11,12 +11,16 @@
 \begin{document}
 
 \frame{\titlepage}
+\note[itemize]{
+\item Small tour: what can we describe in \clash{}
+\item Quick real demo
+}
 
 \include{introduction}
 \include{PolyAlu}
+\include{demo}
 \include{reducer}
 \include{howdoesitwork}
-\include{demo}
 \include{summery}
 
 \end{document}
\ No newline at end of file
diff --git a/clash-haskell09.pdf b/clash-haskell09.pdf
index 19fe325..1600377 100644
Binary files a/clash-haskell09.pdf and b/clash-haskell09.pdf differ
diff --git a/demo.lhs b/demo.lhs
index 834935d..e4f8d48 100644
--- a/demo.lhs
+++ b/demo.lhs
@@ -1,25 +1,26 @@
 \section{Demonstration}
 
 \frame{
-\frametitle{How do we use \clash{}?}
-As a library:
-\begin{itemize}
-  \item Import the module: CLasH.Translator
-  \item And call \emph{makeVHDLAnnotations ghc\_lib\_dir [files\_to\_translate]}
-\end{itemize}
-Customized GHC:
-\begin{itemize}
-  \item Call GHC with the --vhdl flag
-  \item Use the :vhdl command in GHCi
-\end{itemize}
-}
-
-\frame{
-\frametitle{Real Demo}
+\frametitle{Demo}
 \begin{itemize}
   \item We will simulate the small CPU from earlier
-  \item Translate the CPU code to VHDL
+  \item Translate that CPU code to VHDL
   \item Simulate the generated VHDL
-  \item Synthesize the VHDL to get a hardware schematic
+  \item See the hardware schematic of the synthesized VHDL
 \end{itemize}
-}
\ No newline at end of file
+}
+
+% 
+% \frame{
+% \frametitle{How do we use \clash{}?}
+% As a library:
+% \begin{itemize}
+%   \item Import the module: CLasH.Translator
+%   \item And call \emph{makeVHDLAnnotations ghc\_lib\_dir [files\_to\_translate]}
+% \end{itemize}
+% Customized GHC:
+% \begin{itemize}
+%   \item Call GHC with the --vhdl flag
+%   \item Use the :vhdl command in GHCi
+% \end{itemize}
+% }
diff --git a/howdoesitwork.lhs b/howdoesitwork.lhs
index 39137bd..4ad7780 100644
--- a/howdoesitwork.lhs
+++ b/howdoesitwork.lhs
@@ -6,10 +6,13 @@
   \large{In three simple steps} \pause
   \begin{itemize}
     \item No Effort:\\
-    GHC API Parses, Typechecks and Desugars Haskell \pause
-    \item Hard.. sort of: \\
+    GHC API Parses, Typechecks and Desugars the Haskell code \pause
+    \item Hard: \\
     Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form \pause
     \item Easy: \\
     Translate Normalized Core to synthesizable VHDL
   \end{itemize}
+}\note[itemize]{
+\item Here is a quick insight as to how WE translate Haskell to Hardware
+\item You can also use TH, like ForSyDe. Or traverse datastructures, like Lava.
 }
\ No newline at end of file
diff --git a/introduction.lhs b/introduction.lhs
index 32afbe9..b414dac 100644
--- a/introduction.lhs
+++ b/introduction.lhs
@@ -1,16 +1,5 @@
 %include talk.fmt
 \section{Introduction}
-\subsection{What will you see}
-\frame
-{
-  \frametitle{What will we see?}
-  \begin{itemize}
-    \item Small tour: what can we describe in \clash{}
-    \item Quick real demo
-  \end{itemize}
-}
-\note{Virtuele demo}
-
 \subsection{What is \texorpdfstring{\clash{}}{CLasH}}
 \frame
 {
@@ -24,23 +13,25 @@
 }
 \note[itemize]
 {
-\item Wij zijn wij
-\item \clash{} voor rapid prototyping
-\item Subset haskell vertaalbaar
-\item Mealy machine beschrijving
+\item We are a Computer Architectures group, this has been a 6 month project, no prior experience with Haskell.
+\item \clash{} is written in Haskell, of course
+\item \clash{} is currently meant for rapid prototyping, not verification of hardware desigs
+\item Functional languages are close to Hardware
+\item We can only translate a subset of Haskell
+\item All functions are descriptions of Mealy Machines
 }
 
 \subsection{Mealy Machine}
 \frame
 {
-\frametitle{Mealy Machine}
+\frametitle{What again is a Mealy Machine?}
   \begin{figure}
   \centerline{\includegraphics[width=10cm]{mealymachine}}
   \label{img:mealymachine}
   \end{figure}
 }
-\note{
-Voor wie het niet meer weet, dit is een mealy machine
+\note[itemize]{
+\item Mealy machine bases its output on current input and previous state
 }
 
 \frame
@@ -58,7 +49,16 @@ mealyMachine inputs {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3>[rg
     outputs                                         =   logic     {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-}   input
 \end{code}
 \end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item Current state is part of the input}
+\uncover<3->{\item New state is part of the output}
+\end{itemize}
 }
+\note[itemize]{
+\item State is part of the function signature
+\item Both the current state, as the updated State
+}
+
 \subsection{Simulation}
 \frame
 {
@@ -72,4 +72,12 @@ run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out
     out                                             =   run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
 \end{code}
 \end{beamercolorbox}
-}
\ No newline at end of file
+\begin{itemize}
+\item State behaves like an accumulator
+\end{itemize}
+}
+\note[itemize]{
+\item This is just a quick example of how we can simulate the mealy machine
+\item It sort of behaves like MapAccumN
+}
+
diff --git a/polyaluhardware-add.png b/polyaluhardware-add.png
new file mode 100644
index 0000000..83e4c65
Binary files /dev/null and b/polyaluhardware-add.png differ
diff --git a/polyaluhardware-reg.png b/polyaluhardware-reg.png
new file mode 100644
index 0000000..6a49453
Binary files /dev/null and b/polyaluhardware-reg.png differ
diff --git a/polyaluhardware.png b/polyaluhardware.png
new file mode 100644
index 0000000..5a35f06
Binary files /dev/null and b/polyaluhardware.png differ
diff --git a/reducer.lhs b/reducer.lhs
index 09013d1..cf97b3f 100644
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -1,12 +1,16 @@
 \section{Real Hardware Designs}
 \frame{
-\frametitle{Is \clash{} usable?}
+\frametitle{More than just toys}
 \pause
 \begin{itemize}
-  \item It can be used for more than toy examples\pause
   \item We designed a matrix reduction circuit\pause
-  \item We simulated it in Haskell\pause
-  \item Simulation results in VHDL match\pause
+  \item Simulation results in Haskell match VHDL simulation results
   \item Synthesis completes without errors or warnings
+  \item It runs at half the speed of a hand-coded VHDL design
 \end{itemize}
+}\note[itemize]{
+\item Toys like the poly cpu one are good to give a quick demo
+\item But we used \clash{} to design 'real' hardware
+\item Reduction circuit sums the numbers in a row of a (sparse) matrix
+\item Half speed is nice, considering we don't optimize for speed
 }
\ No newline at end of file
diff --git a/summery.lhs b/summery.lhs
index 49248a4..94b11b5 100644
--- a/summery.lhs
+++ b/summery.lhs
@@ -4,16 +4,20 @@
 \frame{
 \frametitle{Some final words}
 \begin{itemize}
-  \item Still a lot to do: make a bigger subset of Haskell translatable
-  \item Real world designs work
-  \item We bring functional expressivity to hardware designs
+  \item Still a lot to do: translate larger subset of Haskell
+  \item Real world prototypes can be made in \clash{}
+  \item \clash{} is another great example of how to bring functional expressivity to hardware designs
 \end{itemize}
 }
 
 \frame{
+\vspace{6em}
 \begin{figure}
 \Huge{Thank you for listening}
 \end{figure}
+\vspace{5em}
+\centerline{\clash{} Clone URL:}
+\centerline{\url{git://github.com/christiaanb/clash.git}}
 }
 
 \frame
@@ -27,4 +31,25 @@ registerBank ::
   (RegState s a) -> a -> RangedWord s ->
   RangedWord s -> Bit -> ((RegState s a), a )
 \end{code}
-}
\ No newline at end of file
+}
+
+\frame{
+\begin{figure}
+\centerline{\includegraphics[width=12cm]{polyaluhardware}}
+\label{img:mealymachine}
+\end{figure}
+}
+
+\frame{
+\begin{figure}
+\centerline{\includegraphics[width=12cm]{polyaluhardware-reg}}
+\label{img:mealymachine}
+\end{figure}
+}
+
+\frame{
+\begin{figure}
+\centerline{\includegraphics[width=12cm]{polyaluhardware-add}}
+\label{img:mealymachine}
+\end{figure}
+}