Fix typos

diff --git a/PolyAlu.hs b/PolyAlu.hs
index a464ffbaea172d76f2c361e6f5f77978dc1ec74c..b9d0da8fc0dba054fad394a4e32e548c42f9154d 100644 (file)
--- a/PolyAlu.hs
+++ b/PolyAlu.hs
@@ -5,27 +5,27 @@ module Main where
 import CLasH.HardwareTypes
 import CLasH.Translator.Annotations
 import qualified Prelude as P
-{-# LINE 51 "PolyAlu.lhs" #-}
+{-# LINE 52 "PolyAlu.lhs" #-}
 type Op a         =   a -> a -> a
-{-# LINE 58 "PolyAlu.lhs" #-}
+type Opcode       =   Bit
+{-# LINE 60 "PolyAlu.lhs" #-}
 type RegBank s a    =   
   Vector (s :+: D1) a
 type RegState s a   =   
   State (RegBank s a)
-{-# LINE 66 "PolyAlu.lhs" #-}
+{-# LINE 68 "PolyAlu.lhs" #-}
 type Word = SizedInt D12
-{-# LINE 85 "PolyAlu.lhs" #-}
-type Opcode         =   Bit
+{-# LINE 88 "PolyAlu.lhs" #-}
 alu :: 
   Op a -> Op a -> 
   Opcode -> a -> a -> a
 alu op1 op2 Low    a b = op1 a b
 alu op1 op2 High   a b = op2 a b
-{-# LINE 108 "PolyAlu.lhs" #-}
+{-# LINE 110 "PolyAlu.lhs" #-}
 registers :: 
   ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s ->
   RangedWord s -> (RegState s a) -> (RegState s a, a )
-{-# LINE 116 "PolyAlu.lhs" #-}
+{-# LINE 118 "PolyAlu.lhs" #-}
 registers data_in rdaddr wraddr (State mem) = 
   ((State mem'), data_out)
   where

diff --git a/reducer.lhs b/reducer.lhs
index 21baeeb9db140eb52b071981ba1403677a7b8313..061f9dbc85da8df260ad574aae2970c988862cab 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -10,7 +10,7 @@
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
-  \item Simulated first Haskell. VHDL simulation results match\pause
+  \item Simulated in Haskell. VHDL simulation results match\pause
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}