X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=blobdiff_plain;f=PolyAlu.hs;fp=PolyAlu.hs;h=8752f955c2aa9044c734fa1d66866dca039d89c1;hp=21f6eff03f2516e9b834e154ec6fb28656e5d3fc;hb=db31ec50d26e4d299f57fe1b15eb60d57ae7d9dd;hpb=715d9487c4e666cef21e89f0735d23a4f5ab2d27

diff --git a/PolyAlu.hs b/PolyAlu.hs
index 21f6eff..8752f95 100644
--- a/PolyAlu.hs
+++ b/PolyAlu.hs
@@ -3,32 +3,32 @@
 module Main where
 
 import qualified Prelude as P
-{-# LINE 29 "PolyAlu.lhs" #-}
+{-# LINE 34 "PolyAlu.lhs" #-}
 import CLasH.HardwareTypes
-{-# LINE 36 "PolyAlu.lhs" #-}
+{-# LINE 41 "PolyAlu.lhs" #-}
 import CLasH.Translator.Annotations
-{-# LINE 48 "PolyAlu.lhs" #-}
+{-# LINE 56 "PolyAlu.lhs" #-}
 type Op s a         =   a -> Vector s a -> a
 type Opcode         =   Bit
-{-# LINE 56 "PolyAlu.lhs" #-}
+{-# LINE 64 "PolyAlu.lhs" #-}
 type RegBank s a    =   Vector (s :+: D1) a
 type RegState s a   =   State (RegBank s a)
-{-# LINE 64 "PolyAlu.lhs" #-}
+{-# LINE 72 "PolyAlu.lhs" #-}
 type Word           =   SizedInt D12
-{-# LINE 76 "PolyAlu.lhs" #-}
+{-# LINE 89 "PolyAlu.lhs" #-}
 primOp :: (a -> a -> a) -> Op s a
 primOp f a b = a `f` a
-{-# LINE 84 "PolyAlu.lhs" #-}
+{-# LINE 97 "PolyAlu.lhs" #-}
 vectOp :: (a -> a -> a) -> Op s a
 vectOp f a b = foldl f a b
-{-# LINE 99 "PolyAlu.lhs" #-}
+{-# LINE 116 "PolyAlu.lhs" #-}
 alu :: 
   Op s a -> 
   Op s a -> 
   Opcode -> a -> Vector s a -> a
 alu op1 op2 Low    a b = op1 a b
 alu op1 op2 High   a b = op2 a b
-{-# LINE 118 "PolyAlu.lhs" #-}
+{-# LINE 139 "PolyAlu.lhs" #-}
 registerBank :: 
   ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
   RangedWord s -> Bit -> ((RegState s a), a )
@@ -39,7 +39,7 @@ registerBank (State mem) data_in rdaddr wraddr wrenable =
     data_out  =   mem!rdaddr
     mem'  | wrenable == Low    = mem
           | otherwise          = replace mem wraddr data_in
-{-# LINE 141 "PolyAlu.lhs" #-}
+{-# LINE 167 "PolyAlu.lhs" #-}
 {-# ANN actual_cpu TopEntity#-}
 actual_cpu :: 
   (Opcode, Word, Vector D4 Word, RangedWord D9, 
@@ -50,7 +50,7 @@ actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
   where
     alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
     (ram',ram_out)  = registerBank ram a rdaddr wraddr wren
-{-# LINE 160 "PolyAlu.lhs" #-}
+{-# LINE 191 "PolyAlu.lhs" #-}
 {-# ANN initstate InitState#-}
 initstate :: RegState D9 Word
 initstate = State (copy (0 :: Word))  
@@ -58,9 +58,9 @@ initstate = State (copy (0 :: Word))
 {-# ANN program TestInput#-}
 program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)]
 program =
-  [ (Low, 4, copy (0::Word), 0, 0, High) --  Write 4 to Reg0, out = 0
-  , (Low, 3, copy (0::Word), 0, 1, High) --  Write 3 to Reg1, out = Reg0 + Reg0 = 8
-  , (High,0, copy (3::Word), 1, 0, Low)  --  No Write       , out = 15
+  [ (Low, 4, copy (0), 0, 0, High) --  Write 4 to Reg0, out = 0
+  , (Low, 3, copy (0), 0, 1, High) --  Write 3 to Reg1, out = 8
+  , (High,0, copy (3), 1, 0, Low)  --  No Write       , out = 15
   ]
 
 run func state [] = []
@@ -74,5 +74,5 @@ main = do
   let input = program
   let istate = initstate
   let output = run actual_cpu istate input
-  mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output
+  mapM_ (\x -> putStr $ ("(" P.++ (show x) P.++ ")\n")) output
   return ()