From 0122d3411d9ac2f74e77e1f5b2730ae1968c2ac2 Mon Sep 17 00:00:00 2001 From: Christiaan Baaij Date: Wed, 3 Mar 2010 14:28:51 +0100 Subject: [PATCH] Reverse state and inputs in higher-order cpu --- "c\316\273ash.lhs" | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git "a/c\316\273ash.lhs" "b/c\316\273ash.lhs" index 95c7738..3d4dfad 100644 --- "a/c\316\273ash.lhs" +++ "b/c\316\273ash.lhs" @@ -1203,17 +1203,18 @@ fu op inputs (addr1, addr2) = regIn \end{code} \begin{code} -cpu :: Word -> [(Index 6, Index 6) | 4] - -> State [Word | 4] -> (State [Word | 4], Word) -cpu input addrs (State fuss) = (State fuss', out) +cpu :: State [Word | 4] -> Word + -> [(Index 6, Index 6) | 4] + -> (State [Word | 4], Word) +cpu (State regsOut) input addrs = (State regsIn, out) where - fuss' = [ fu const inputs (addrs!0) - , fu (+) inputs (addrs!1) - , fu (-) inputs (addrs!2) - , fu (*) inputs (addrs!3) - ] - inputs = 0 +> (1 +> (input +> fuss)) - out = head fuss + regsIn = [ fu const inputs (addrs!0) + , fu (+) inputs (addrs!1) + , fu (-) inputs (addrs!2) + , fu (*) inputs (addrs!3) + ] + inputs = 0 +> (1 +> (input +> regsOut)) + out = head regsOut \end{code} \section{Related work} -- 2.30.2