X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fdsd-paper.git;a=blobdiff_plain;f=clash.bib;h=d9c222526d62f7b865bacaa9a76c194a3800acf0;hp=6df0a8609745c8005652ab6b495536638b99c881;hb=873181fb5443e30352ce819956fdac9a45e28faa;hpb=52eaf8cbf614a5bdd3e3804ce72263fae2b9d024

diff --git a/clash.bib b/clash.bib
index 6df0a86..d9c2225 100644
--- a/clash.bib
+++ b/clash.bib
@@ -50,6 +50,72 @@
   timestamp = {2010.01.20}
 }
 
+@INPROCEEDINGS{reductioncircuit,
+  author = {M. E. T. Gerards and J. Kuper and A. B. J. Kokkeler and E. Molenkamp},
+  title = {Streaming Reduction Circuit},
+  booktitle = {Proceedings of the 12th EUROMICRO Conference on Digital System Design,
+	Architectures, Methods and Tools, Patras, Greece},
+  year = {2009},
+  pages = {287--292},
+  address = {Los Alamitos},
+  month = {August},
+  publisher = {IEEE Computer Society Press},
+  abstract = {Reduction circuits are used to reduce rows of ?oating point values
+	to single values. Binary ?oating point operators often have deep
+	pipelines, which may cause hazards when many consecutive rows have
+	to be reduced. We present an algorithm by which any number of consecutive
+	rows of arbitrary lengths can be reduced by a pipelined commutative
+	and associative binary operator in an efficient manner. The algorithm
+	is simple to implement, has a low latency, produces results in-order,
+	and requires only small buffers. Besides, it uses only a single pipeline
+	for the involved operation. The complexity of the algorithm depends
+	on the depth of the pipeline, not on the length of the input rows.
+	In this paper we discuss an implementation of this algorithm and
+	we prove its correctness.},
+  eprintid = {17041},
+  event_dates = {27-29 Aug 2009},
+  event_type = {Conference},
+  howpublished = {http://eprints.eemcs.utwente.nl/17041/},
+  id_number = {10.1109/DSD.2009.141},
+  international = {Yes},
+  isbn_13 = {978-0-7695-3782-5},
+  ispublished = {Published},
+  location = {Patras, Greece},
+  num_pages = {6},
+  official_url = {http://dx.doi.org/10.1109/DSD.2009.141},
+  owner = {baaijcpr},
+  pres_types = {Talk},
+  refereed = {Yes},
+  research_groups = {EWI-CAES: Computer Architecture for Embedded Systems},
+  research_programs = {CTIT-WiSe: Wireless and Sensor Systems},
+  research_projects = {EASY: Embedded Adaptive Streaming sYstems},
+  timestamp = {2010.02.26}
+}
+
+@UNPUBLISHED{kansaslava,
+  author = {Andy Gill and T. Bull and Garrin Kimmell and Erik Perrins and Ed
+	Komp and B. Werling},
+  title = {Introducing Kansas Lava},
+  note = {Submitted to The International Symposia on Implementation and Application
+	of Functional Languages (IFL){\textquoteright}09},
+  month = {November},
+  year = {2009},
+  abstract = {Kansas Lava is a domain specific language for hardware description.
+	Though there have been a number of previous implementations of Lava,
+	we have found the design space rich, with unexplored choices. We
+	use a direct (Chalmers style) specification of circuits, and make
+	significant use of Haskell overloading of standard classes, leading
+	to concise circuit descriptions. Kansas Lava supports both simulation
+	(inside GHCi), and execution via VHDL, by having a dual shallow and
+	deep embedding inside our Signal type. We also have a lightweight
+	sized-type mechanism, allowing for MATLAB style matrix based specifications
+	to be directly expressed in Kansas Lava.},
+  journal = {Submitted to IFL{\textquoteright}09},
+  owner = {baaijcpr},
+  timestamp = {2010.03.11},
+  url = {http://ittc.ku.edu/~andygill/papers/kansas-lava-ifl09.pdf}
+}
+
 @ARTICLE{reFLect,
   author = {Grundy,Jim and Melham,Tom and O'Leary,John},
   title = {{A reflective functional language for hardware design and theorem
@@ -64,6 +130,18 @@
   timestamp = {2010.01.21}
 }
 
+@BOOK{lambdacalculus,
+  title = {{The Lambda Calculus: its Syntax and Semantics}},
+  publisher = {{Elsevier Science}},
+  year = {1984},
+  author = {{H.P. Barendregt}},
+  volume = {103},
+  series = {{Studies in Logic and the Foundations of Mathematics}},
+  edition = {{Revised}},
+  owner = {baaijcpr},
+  timestamp = {2010.03.02}
+}
+
 @INPROCEEDINGS{DAISY,
   author = {Johnson, Steven D.},
   title = {Applicative programming and digital design},
@@ -96,6 +174,17 @@
   timestamp = {2010.01.20}
 }
 
+@MASTERSTHESIS{HML3,
+  author = {Yanbing Li},
+  title = {{HML: An Innovative Hardware Description Language and Its Translation
+	to VHDL}},
+  school = {Cornell University},
+  year = {1995},
+  month = {August},
+  owner = {baaijcpr},
+  timestamp = {2010.03.08}
+}
+
 @ARTICLE{HML2,
   author = {Yanbing Li and Leeser, M.},
   title = {{HML, a novel hardware description language and its translation to
@@ -208,6 +297,19 @@
   timestamp = {2010.01.25}
 }
 
+@INCOLLECTION{Bluespec,
+  author = {Rishiyur S. Nikhil},
+  title = {{Bluespec: A General-Purpose Approach to High-Level Synthesis Based
+	on Parallel Atomic Transactions}},
+  booktitle = {{High-Level Synthesis - From Algorithm to Digital Circuit}},
+  publisher = {Springer Netherlands},
+  year = {2008},
+  editor = {{Philippe Coussy and Adam Morawiec}},
+  pages = {129--146},
+  owner = {baaijcpr},
+  timestamp = {2010.03.09}
+}
+
 @INPROCEEDINGS{Hydra,
   author = {John O'Donnell},
   title = {{From Transistors to Computer Architecture: Teaching Functional Circuit
@@ -299,6 +401,24 @@
   timestamp = {2010.02.24}
 }
 
+@INPROCEEDINGS{Sulzmann2007,
+  author = {Sulzmann, Martin and Chakravarty, Manuel M. T. and Jones, Simon Peyton
+	and Donnelly, Kevin},
+  title = {{System F with Type Equality Coercions}},
+  booktitle = {{TLDI '07: Proceedings of the 2007 ACM SIGPLAN international workshop
+	on Types in languages design and implementation, Nice, France}},
+  year = {2007},
+  pages = {53--66},
+  address = {{New York, NY, USA}},
+  month = {January},
+  publisher = {{ACM}},
+  doi = {http://doi.acm.org/10.1145/1190315.1190324},
+  isbn = {1-59593-393-X},
+  location = {Nice, Nice, France},
+  owner = {darchon},
+  timestamp = {2009.10.23}
+}
+
 @ELECTRONIC{ghc,
   author = {{The GHC Team}},
   title = {{The Glasgow Haskell Compiler}},
@@ -321,6 +441,12 @@
   timestamp = {2010.01.29}
 }
 
+@MISC{blindreview,
+  title = {Hidden for blind review},
+  owner = {baaijcpr},
+  timestamp = {2010.03.12}
+}
+
 @STANDARD{VHDL2008,
   title = {{VHDL Language Reference Manual}},
   organization = {IEEE},