X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fdsd-paper.git;a=blobdiff_plain;f=c%CE%BBash.lhs;h=9fb964773a948b737ee7055d4e86500b3202a3c5;hp=3bcf41e75f41e3a0d507925cf1b78ea005e7b251;hb=8cf5b5c041beee1dd39678bc70b7ec934ecc4d98;hpb=04826a331fd930f2657850390efe332f18c40424

diff --git "a/c\316\273ash.lhs" "b/c\316\273ash.lhs"
index 3bcf41e..9fb9647 100644
--- "a/c\316\273ash.lhs"
+++ "b/c\316\273ash.lhs"
@@ -762,7 +762,7 @@ circuit~\cite{reductioncircuit} for floating point numbers.
         the rest of paper is: \hs{[a|n]}. Where the \hs{a} is the element 
         type, and \hs{n} is the length of the vector. Note that this is
         a notation used in this paper only, vectors are slightly more
-        elaborate in real \CLaSH\ programs.
+        verbose in real \CLaSH\ descriptions.
         % The state type of an 8 element register bank would then for example 
         % be:
 
@@ -1192,12 +1192,11 @@ the vectors of the \acro{FIR} code to a length of 4, is depicted in
 \subsection{Higher order CPU}
 
 \begin{code}
-fu op inputs (addr1, addr2) (State out) =
-  (State out', out)
+fu op inputs (addr1, addr2) = regIn
   where
-    in1  = inputs!addr1
-    in2  = inputs!addr2
-    out' = op in1 in2
+    in1     = inputs!addr1
+    in2     = inputs!addr2
+    regIn   = op in1 in2
 \end{code}
 
 \begin{code}
@@ -1205,14 +1204,13 @@ cpu :: Word -> [(Index 6, Index 6) | 4]
   -> State [Word | 4] -> (State [Word | 4], Word)
 cpu input addrs (State fuss) = (State fuss', out)
   where
-    fures =   [ fu const  inputs (addrs!0) (fuss!0)
+    fuss' =   [ fu const  inputs (addrs!0) (fuss!0)
               , fu (+)    inputs (addrs!1) (fuss!1)
               , fu (-)    inputs (addrs!2) (fuss!2)
               , fu (*)    inputs (addrs!3) (fuss!3)
               ]
-    (fuss', outputs)  = unzip fures
-    inputs            = 0 +> (1 +> (input +> outputs))
-    out               = head outputs
+    inputs    = 0 +> (1 +> (input +> fuss))
+    out       = head fuss
 \end{code}
 
 \section{Related work}