X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fdsd-paper.git;a=blobdiff_plain;f=c%CE%BBash.lhs;h=2fa6b8615ff78ce701ecefb496b9223b1bd57bbb;hp=59f529ad461d1155ad630af3905257b0175780e3;hb=645d4f8e703fcb77044b0fce5b3134187ef056aa;hpb=65363f98c6333631868a58c2756ba53614c59cc6

diff --git "a/c\316\273ash.lhs" "b/c\316\273ash.lhs"
index 59f529a..2fa6b86 100644
--- "a/c\316\273ash.lhs"
+++ "b/c\316\273ash.lhs"
@@ -1192,12 +1192,11 @@ the vectors of the \acro{FIR} code to a length of 4, is depicted in
 \subsection{Higher order CPU}
 
 \begin{code}
-fu op inputs (addr1, addr2) (State out) =
-  (State out', out)
+fu op inputs (addr1, addr2) regOut = (regIn, regOut)
   where
-    in1  = inputs!addr1
-    in2  = inputs!addr2
-    out' = op in1 in2
+    in1     = inputs!addr1
+    in2     = inputs!addr2
+    regIn   = op in1 in2
 \end{code}
 
 \begin{code}