X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fdsd-paper.git;a=blobdiff_plain;f=c%CE%BBash.lhs;h=074ec9141aaba6535eb217a47d4cc010ba931ce2;hp=a9de945ea7659b65e6251a930a7f81db5ea776b5;hb=9d6ed84c8d147725d8d8cf4deac9ca07869cbf3b;hpb=f5c0a08b8c7c946a9e10fedc0d5ae52675407db4

diff --git "a/c\316\273ash.lhs" "b/c\316\273ash.lhs"
index a9de945..074ec91 100644
--- "a/c\316\273ash.lhs"
+++ "b/c\316\273ash.lhs"
@@ -400,7 +400,7 @@
 Department of EEMCS, University of Twente\\
 P.O. Box 217, 7500 AE, Enschede, The Netherlands\\
 c.p.r.baaij@@utwente.nl, matthijs@@stdin.nl, j.kuper@@utwente.nl}
-% \thanks{Supported through FP7 project: S(o)OS (248465)}
+\thanks{Supported through the FP7 project: S(o)OS (248465)}
 }
 % \and
 % \IEEEauthorblockN{Homer Simpson}
@@ -452,14 +452,21 @@ c.p.r.baaij@@utwente.nl, matthijs@@stdin.nl, j.kuper@@utwente.nl}
 \begin{abstract}
 %\boldmath
 \CLaSH\ is a functional hardware description language that borrows both its 
-syntax and semantics from the functional programming language Haskell. Circuit 
-descriptions can be translated to synthesizable VHDL using the prototype 
-\CLaSH\ compiler. As the circuit descriptions are made in plain Haskell, 
-simulations can also be compiled by a Haskell compiler.
-
-The use of polymorphism and higher-order functions allow a circuit designer to 
-describe more abstract and general specifications than are possible in the 
-traditional hardware description languages.
+syntax and semantics from the functional programming language Haskell. Due to 
+the abstraction and generality offered by polymorphism and higher-order 
+functions, a circuit designer can describe circuits in a more natural way than 
+he could in the traditional hardware description languages.
+
+Circuit descriptions can be translated to synthesizable VHDL using the 
+prototype \CLaSH\ compiler. As the circuit descriptions, simulation code, and 
+test input are plain Haskell, complete simulations can be compiled to an 
+executable binary by a Haskell compiler allowing high-speed simulation and 
+analysis.
+
+Stateful descriptions are supported by explicitly making the current state an 
+argument of the function, and the updated state part of the result. In this 
+sense, the descriptions made in \CLaSH\ are the combinational parts of a mealy 
+machine.
 \end{abstract}
 % IEEEtran.cls defaults to using nonbold math in the Abstract.
 % This preserves the distinction between vectors and scalars. However,
@@ -1203,9 +1210,10 @@ fu op inputs (addr1, addr2) = regIn
 \end{code}
 
 \begin{code}
-cpu :: State [Word | 4] -> Word 
-  -> [(Index 6, Index 6) | 4]
-  -> (State [Word | 4], Word)
+type CpuState = State [Word | 4]
+
+cpu :: CpuState -> Word -> [(Index 6, Index 6) | 4]
+  -> (CpuState, Word)
 cpu (State regsOut) input addrs = (State regsIn, out)
   where
     regsIn    =   [ fu const  inputs (addrs!0)
@@ -1415,7 +1423,7 @@ earlier mentioned properties do indeed exist.
 % number - used to balance the columns on the last page
 % adjust value as needed - may need to be readjusted if
 % the document is modified later
-%\IEEEtriggeratref{8}
+\IEEEtriggeratref{14}
 % The "triggered" command can be changed if desired:
 %\IEEEtriggercmd{\enlargethispage{-5in}}