Update VHDL-2008 part in related work section

[matthijs/master-project/dsd-paper.git] / cλash.lhs

diff --git a/cλash.lhs b/cλash.lhs
index 3bcf41e75f41e3a0d507925cf1b78ea005e7b251..1b3dc1323f3e7fc61ce227c2d6f1c63bf6424273 100644 (file)
--- a/cλash.lhs
+++ b/cλash.lhs
@@ -762,7 +762,7 @@ circuit~\cite{reductioncircuit} for floating point numbers.
         the rest of paper is: \hs{[a|n]}. Where the \hs{a} is the element 
         type, and \hs{n} is the length of the vector. Note that this is
         a notation used in this paper only, vectors are slightly more
-        elaborate in real \CLaSH\ programs.
+        verbose in real \CLaSH\ descriptions.
         % The state type of an 8 element register bank would then for example 
         % be:
 
@@ -1192,12 +1192,11 @@ the vectors of the \acro{FIR} code to a length of 4, is depicted in
 \subsection{Higher order CPU}
 
 \begin{code}
-fu op inputs (addr1, addr2) (State out) =
-  (State out', out)
+fu op inputs (addr1, addr2) = regIn
   where
-    in1  = inputs!addr1
-    in2  = inputs!addr2
-    out' = op in1 in2
+    in1     = inputs!addr1
+    in2     = inputs!addr2
+    regIn   = op in1 in2
 \end{code}
 
 \begin{code}
@@ -1205,14 +1204,13 @@ cpu :: Word -> [(Index 6, Index 6) | 4]
   -> State [Word | 4] -> (State [Word | 4], Word)
 cpu input addrs (State fuss) = (State fuss', out)
   where
-    fures =   [ fu const  inputs (addrs!0) (fuss!0)
+    fuss' =   [ fu const  inputs (addrs!0) (fuss!0)
               , fu (+)    inputs (addrs!1) (fuss!1)
               , fu (-)    inputs (addrs!2) (fuss!2)
               , fu (*)    inputs (addrs!3) (fuss!3)
               ]
-    (fuss', outputs)  = unzip fures
-    inputs            = 0 +> (1 +> (input +> outputs))
-    out               = head outputs
+    inputs    = 0 +> (1 +> (input +> fuss))
+    out       = head fuss
 \end{code}
 
 \section{Related work}
@@ -1274,11 +1272,7 @@ mentioned in this section.
 The merits of polymorphic typing, combined with higher-order functions, are 
 now also recognized in the `main-stream' hardware description languages, 
 exemplified by the new \VHDL-2008 standard~\cite{VHDL2008}. \VHDL-2008 support 
-for generics has been extended to types, allowing a developer to describe 
-polymorphic components. Note that those types still require an explicit 
-generic map, whereas types can be automatically inferred in \CLaSH. There are 
-also no (generally available) \VHDL\ synthesis tools that currently support 
-the \VHDL-2008 standard, and thus the synthesis of polymorphic types.
+for generics has been extended to types and subprograms, allowing a developer to describe components with polymorphic ports and function-valued arguments. Note that the types and subprograms still require an explicit generic map, whereas types can be automatically inferred, and function-values can be automatically propagated by the \CLaSH\ compiler. There are also no (generally available) \VHDL\ synthesis tools that currently support the \VHDL-2008 standard, and thus the synthesis of polymorphic types and function-valued arguments.
 
 % Wired~\cite{Wired},, T-Ruby~\cite{T-Ruby}, Hydra~\cite{Hydra}. 
 %