%
\documentclass[conference,pdf,a4paper,10pt,final,twoside,twocolumn]{IEEEtran}
+\IEEEoverridecommandlockouts
% Add the compsoc option for Computer Society conferences.
%
% If IEEEtran.cls has not been installed into the LaTeX system files,
% Macro for certain acronyms in small caps. Doesn't work with the
% default font, though (it contains no smallcaps it seems).
\def\acro#1{{\small{#1}}}
+\def\acrop#1{\acro{#1}s}
\def\acrotiny#1{{\scriptsize{#1}}}
\def\VHDL{\acro{VHDL}}
\def\GHC{\acro{GHC}}
\IEEEauthorblockA{%Computer Architecture for Embedded Systems (CAES)\\
Department of EEMCS, University of Twente\\
P.O. Box 217, 7500 AE, Enschede, The Netherlands\\
-c.p.r.baaij@@utwente.nl, matthijs@@stdin.nl, j.kuper@@utwente.nl}}
+c.p.r.baaij@@utwente.nl, matthijs@@stdin.nl, j.kuper@@utwente.nl}
+% \thanks{Supported through the FP7 project: S(o)OS (248465)}
+}
% \and
% \IEEEauthorblockN{Homer Simpson}
% \IEEEauthorblockA{Twentieth Century Fox\\
% make the title area
\maketitle
-
\begin{abstract}
%\boldmath
\CLaSH\ is a functional hardware description language that borrows both its
-syntax and semantics from the functional programming language Haskell. Circuit
-descriptions can be translated to synthesizable VHDL using the prototype
-\CLaSH\ compiler. As the circuit descriptions are made in plain Haskell,
-simulations can also be compiled by a Haskell compiler.
-
-The use of polymorphism and higher-order functions allow a circuit designer to
-describe more abstract and general specifications than are possible in the
-traditional hardware description languages.
+syntax and semantics from the functional programming language Haskell.
+Polymorphism and higher-order functions provide a level of abstraction and
+generality that allow a circuit designer to describe circuits in a more
+natural way than possible in a traditional hardware description language.
+
+Circuit descriptions can be translated to synthesizable VHDL using the
+prototype \CLaSH\ compiler. As the circuit descriptions, simulation code, and
+test input are also valid Haskell, complete simulations can be compiled as an
+executable binary by a Haskell compiler allowing high-speed simulation and
+analysis.
+
+Stateful descriptions are supported by explicitly making the current state an
+argument of the function, and the updated state part of the result. In this
+sense, \CLaSH\ descriptions are the combinational parts of a mealy machine.
\end{abstract}
% IEEEtran.cls defaults to using nonbold math in the Abstract.
% This preserves the distinction between vectors and scalars. However,
% creates the second title. It will be ignored for other modes.
\IEEEpeerreviewmaketitle
-
\section{Introduction}
-Hardware description languages have allowed the productivity of hardware
-engineers to keep pace with the development of chip technology. Standard
-Hardware description languages, like \VHDL~\cite{VHDL2008} and
-Verilog~\cite{Verilog}, allowed an engineer to describe circuits using a
-programming language. These standard languages are very good at describing
-detailed hardware properties such as timing behavior, but are generally
-cumbersome in expressing higher-level abstractions. In an attempt to raise the
-abstraction level of the descriptions, a great number of approaches based on
-functional languages has been proposed \cite{T-Ruby,Hydra,HML2,Hawk1,Lava,
-ForSyDe1,Wired,reFLect}. The idea of using functional languages for hardware
-descriptions started in the early 1980s \cite{Cardelli1981, muFP,DAISY,FHDL},
-a time which also saw the birth of the currently popular hardware description
-languages such as \VHDL. Functional languages are especially suited to
-describe hardware because combinational circuits can be directly modeled
-as mathematical functions and that functional languages are very good at
-describing and composing mathematical functions.
+Hardware description languages (\acrop{HDL}) have allowed the productivity of
+hardware engineers to keep pace with the development of chip technology.
+Standard \acrop{HDL}, like \VHDL~\cite{VHDL2008} and Verilog~\cite{Verilog},
+allowed an engineer to describe circuits using a `programming' language. These
+standard languages are very good at describing detailed hardware properties
+such as timing behavior, but are generally cumbersome in expressing
+higher-level abstractions. In an attempt to raise the abstraction level of the
+descriptions, a great number of approaches based on functional languages has
+been proposed \cite{Cardelli1981, muFP,DAISY,FHDL,T-Ruby,Hydra,HML2,Hawk1,
+Lava,ForSyDe1,Wired,reFLect}. The idea of using functional languages for
+hardware descriptions started in the early 1980s \cite{Cardelli1981,muFP,
+DAISY,FHDL}, a time which also saw the birth of the currently popular hardware
+description languages such as \VHDL. Functional languages are especially well
+suited to describe hardware because combinational circuits can be directly
+modeled as mathematical functions. Furthermore, functional languages are very
+good at describing and composing mathematical functions.
In an attempt to decrease the amount of work involved in creating all the
required tooling, such as parsers and type-checkers, many functional
-hardware description languages \cite{Hydra,Hawk1,Lava,ForSyDe1,Wired}
-are embedded as a domain specific language inside the functional
-language Haskell \cite{Haskell}. This means that a developer is given a
-library of Haskell functions and types that together form the language
-primitives of the domain specific language. The primitive functions used
-to describe a circuit do not actually process any signals, but instead
-compose a large domain-specific datatype (which is usually hidden from
-the designer). This datatype is then further processed by an embedded
-circuit compiler. This circuit compiler actually runs in the same
-environment as the description; as a result compile-time and run-time
-become hard to define, as the embedded circuit compiler is usually
-compiled by the same Haskell compiler as the circuit description itself.
-
-The approach taken in this research is not to make another domain specific
-language embedded in Haskell, but to use (a subset of) the Haskell language
-itself for the purpose of describing hardware. By taking this approach, we can
+\acrop{HDL} \cite{Hydra,Hawk1,Lava,ForSyDe1,Wired} are embedded as a domain
+specific language (\acro{DSL}) inside the functional language Haskell
+\cite{Haskell}. This means that a developer is given a library of Haskell
+functions and types that together form the language primitives of the
+\acro{DSL}. The primitive functions used to describe a circuit do not actually
+process any signals, but instead compose a large domain-specific datatype
+(which is usually hidden from the designer). This datatype is then further
+processed by an embedded circuit compiler. This circuit compiler actually
+runs in the same environment as the description; as a result compile-time and
+run-time become hard to define, as the embedded circuit compiler is usually
+compiled by the same Haskell compiler as the circuit description itself.
+Though the embedded language approach still allows for the support of
+polymorphism and higher-order functions, it impossible to capture Haskell's
+choice elements within a circuit description.
+
+The approach taken in this research is not to make another \acro{DSL} embedded
+in Haskell, but to use (a subset of) the Haskell language \emph{itself} for
+the purpose of describing hardware. By taking this approach, we \emph{can}
capture certain language constructs, such as Haskell's choice elements
-(if-expressions, case-expressions, pattern matching, etc.), which are not
-available in the functional hardware description languages that are embedded
-in Haskell as a domain specific language. As far as the authors know, such
-extensive support for choice-elements is new in the domain of functional
-hardware description languages. As the hardware descriptions are plain Haskell
-functions, these descriptions can be compiled to an executable binary
-for simulation using an optimizing Haskell compiler such as the Glasgow
-Haskell Compiler (\GHC)~\cite{ghc}.
-
-Where descriptions in a conventional hardware description language have an
-explicit clock for the purpose state and synchronicity, the clock is implied
-in this research. A developer describes the behavior of the hardware between
-clock cycles. Many functional hardware description model signals as a stream
-of all values over time; state is then modeled as a delay on this stream of
-values. The approach taken in this research is to make the current state of a
-circuit part of the input of the function and the updated state part of the
-output. The current abstraction of state and time limits the descriptions to
-synchronous hardware, there however is room within the language to eventually
-add a different abstraction mechanism that will allow for the modeling of
-asynchronous systems.
-
-Like the standard hardware description languages, descriptions made in a
-functional hardware description language must eventually be converted into a
-netlist. This research also features a prototype translator, which has the
-same name as the language: \CLaSH\footnote{\CLaSHtiny: \acrotiny{CAES}
-Language for Synchronous Hardware} (pronounced: clash). This compiler converts
-the Haskell code to equivalently behaving synthesizable \VHDL\ code, ready to
-be converted to an actual netlist format by an (optimizing) \VHDL\ synthesis
-tool.
-
-Besides trivial circuits such as variants of both the FIR filter and the
-simple CPU shown in \Cref{sec:usecases}, the \CLaSH\ compiler has also been
-shown to work for non-trivial descriptions. \CLaSH\ has been able to
-successfully translate the functional description of a streaming reduction
-circuit~\cite{reductioncircuit} for floating point numbers.
+(\hs{if}-expressions, \hs{case}-expressions, pattern matching, etc.), within
+circuit descriptions. To the best knowledge of the authors, supporting
+polymorphism, higher-order functions and such an extensive array of
+choice-elements is new in the domain of functional \acrop{HDL}.
+% As the hardware descriptions are plain Haskell
+% functions, these descriptions can be compiled to an executable binary
+% for simulation using an optimizing Haskell compiler such as the Glasgow
+% Haskell Compiler (\GHC)~\cite{ghc}.
+
+Where descriptions in a conventional \acro{HDL} have an explicit clock for the
+purposes state and synchronicity, the clock is implied in the context of the
+research presented in this paper. A circuit designer describes the behavior of
+the hardware between clock cycles. Many functional \acrop{HDL} model signals
+as a stream of all values over time; state is then modeled as a delay on this
+stream of values. The approach taken in this research is to make the current
+state of a circuit part of the input of the function and the updated state
+part of the output. The current abstraction of state and time limits the
+descriptions to synchronous hardware, there is however room within the
+language to eventually add a different abstraction mechanism that will allow
+for the modeling of asynchronous systems.
+
+Like the traditional \acrop{HDL}, descriptions made in a functional \acro{HDL}
+must eventually be converted into a netlist. This research also features a
+prototype translator, which has the same name as the language:
+\CLaSH\footnote{\CLaSHtiny: \acrotiny{CAES} Language for Synchronous Hardware}
+(pronounced: clash). This compiler converts the Haskell code to equivalently
+behaving synthesizable \VHDL\ code, ready to be converted to an actual netlist
+format by an (optimizing) \VHDL\ synthesis tool.
+
+Besides trivial circuits such as variants of both the \acro{FIR} filter and
+the simple \acro{CPU} shown in \Cref{sec:usecases}, the \CLaSH\ compiler has
+also been able to successfully translate non-trivial functional descriptions
+such as a streaming reduction circuit~\cite{reductioncircuit} for floating
+point numbers.
\section{Hardware description in Haskell}
\subsection{Function application}
- The basic syntactic elements of a functional program are functions
+ Two basic syntactic elements of a functional program are functions
and function application. These have a single obvious translation to a
netlist format:
\begin{inparaenum}
and
\item function applications are translated to component instantiations.
\end{inparaenum}
- The output port can have a structured type (such as a tuple), so having
- just a single output port does not pose any limitation. The actual
+ The result value can have a composite type (such as a tuple), so having
+ just a single result value does not pose any limitation. The actual
arguments of a function application are assigned to signals, which are
then mapped to the corresponding input ports of the component. The output
port of the function is also mapped to a signal, which is used as the
- result of the application itself.
-
- Since every top level function generates its own component, the
- hierarchy of function calls is reflected in the final netlist,% aswell,
- creating a hierarchical description of the hardware. The separation in
- different components makes it easier for a developer to understand and
- possibly hand-optimize the resulting \VHDL\ output of the \CLaSH\
- compiler.
-
- As an example we can see the netlist of the |mac| function in
- \Cref{img:mac-comb}; the |mac| function applies both the |mul| and |add|
- function to calculate $a * b + c$:
+ result of the application itself. Since every top level function generates
+ its own component, the hierarchy of function calls is reflected in the
+ final netlist, creating a hierarchical description of the hardware.
+ % The separation in different components makes it easier for a developer
+ % to understand and possibly hand-optimize the resulting \VHDL\ output of
+ % the \CLaSH\ compiler.
+
+ The short example demonstrated below gives an indication of the level of
+ conciseness that can be achieved with functional hardware description
+ languages when compared with the more traditional hardware description
+ languages. The example is a combinational multiply-accumulate circuit that
+ works for \emph{any} word length (this type of polymorphism will be
+ further elaborated in \Cref{sec:polymorhpism}). The corresponding netlist
+ is depicted in \Cref{img:mac-comb}.
\begin{code}
mac a b c = add (mul a b) c
\label{img:mac-comb}
\end{figure}
- The result of using a structural input type can be seen in
- \cref{img:mac-comb-nocurry} where the |mac| function now uses a single
- input tuple for the |a|, |b|, and |c| arguments:
+ The use of a composite result value is demonstrated in the next example,
+ where the multiply-accumulate circuit not only returns the accumulation
+ result, but also the intermediate multiplication result. Its corresponding
+ netlist can be see in \Cref{img:mac-comb-composite}.
\begin{code}
- mac (a, b, c) = add (mul a b) c
+ mac a b c = (z, add z c)
+ where
+ z = mul a b
\end{code}
\begin{figure}
\centerline{\includegraphics{mac-nocurry.svg}}
- \caption{Combinatorial Multiply-Accumulate (complex input)}
- \label{img:mac-comb-nocurry}
+ \caption{Combinatorial Multiply-Accumulate (composite output)}
+ \label{img:mac-comb-composite}
\end{figure}
\subsection{Choice}
\end{code}
The naive netlist corresponding to both versions of the example is
- depicted in \Cref{img:choice}.
+ depicted in \Cref{img:choice}. Note that the \hs{pred} variable is only
+ compared to the \hs{Equal} value, as an inequality immediately implies
+ that the \hs{pred} variable has a \hs{NotEqual} value.
\begin{code}
sumif pred a b = case pred of
\label{img:choice}
\end{figure}
- A user-friendly and also very powerful form of choice is pattern
- matching. A function can be defined in multiple clauses, where each clause
- corresponds to a pattern. When an argument matches a pattern, the
- corresponding clause will be used. Expressions can also contain guards,
- where the expression is only executed if the guard evaluates to true, and
- continues with the next clause if the guard evaluates to false. Like
- \hs{if-then-else} expressions, pattern matching and guards have a
- (straightforward) translation to \hs{case} expressions and can as such be
- mapped to multiplexers. A third version of the earlier example, using both
- pattern matching and guards, can be seen below. The guard is the
- expression that follows the vertical bar (\hs{|}) and precedes the
- assignment operator (\hs{=}). The \hs{otherwise} guards always evaluate to
- \hs{true}.
+ A user-friendly and also very powerful form of choice that is not found in
+ the traditional hardware description languages is pattern matching. A
+ function can be defined in multiple clauses, where each clause corresponds
+ to a pattern. When an argument matches a pattern, the corresponding clause
+ will be used. Expressions can also contain guards, where the expression is
+ only executed if the guard evaluates to true, and continues with the next
+ clause if the guard evaluates to false. Like \hs{if-then-else}
+ expressions, pattern matching and guards have a (straightforward)
+ translation to \hs{case} expressions and can as such be mapped to
+ multiplexers. A third version of the earlier example, using both pattern
+ matching and guards, can be seen below. The guard is the expression that
+ follows the vertical bar (\hs{|}) and precedes the assignment operator
+ (\hs{=}). The \hs{otherwise} guards always evaluate to \hs{true}.
The version using pattern matching and guards corresponds to the same
naive netlist representation (\Cref{img:choice}) as the earlier two
compiler. The \CLaSH\ compiler has generic translation rules to
translated the user-defined types described below.
- The \CLaSH compiler is able to infer unspecified types,
+ The \CLaSH\ compiler is able to infer unspecified types,
meaning that a developer does not have to annotate every function with a
- type signature (though it is good practice to do so anyway).
+ type signature (even if it is good practice to do so).
% Translation of two most basic functional concepts has been
% discussed: function application and choice. Before looking further
has a fixed length. The \hs{Vector} type constructor takes two type
arguments: the length of the vector and the type of the elements
contained in it. The short-hand notation used for the vector type in
- the rest of paper is: \hs{[a|n]}. Where the \hs{a} is the element
+ the rest of paper is: \hs{[a|n]}, here \hs{a} is the element
type, and \hs{n} is the length of the vector. Note that this is
a notation used in this paper only, vectors are slightly more
- elaborate in real \CLaSH programs.
+ verbose in real \CLaSH\ descriptions.
% The state type of an 8 element register bank would then for example
% be:
names for existing types, where synonyms are completely interchangeable
and type renaming requires explicit conversions. Therefore, these do not
need any particular translation, a synonym or renamed type will just use
- the same representation as the original type. For algebraic types, we can
- make the following distinctions:
-
+ the same representation as the original type.
+
+ For algebraic types, we can make the following distinctions:
\begin{xlist}
\item[\bf{Single constructor}]
Algebraic datatypes with a single constructor with one or more
supported.
\end{xlist}
- \subsection{Polymorphism}
+ \subsection{Polymorphism}\label{sec:polymorhpism}
A powerful feature of most (functional) programming languages is
polymorphism, it allows a function to handle values of different data
types in a uniform way. Haskell supports \emph{parametric
consequently there is no way to determine the actual types for the type
parameters.
- \CLaSH\ does not support user-defined type classes, but does use some
- of the standard Haskell type classes for its built-in function, such as:
- \hs{Num} for numerical operations, \hs{Eq} for the equality operators, and
- \hs{Ord} for the comparison/order operators.
+ \CLaSH\ does \emph{currently} not support\emph{ user-defined} type
+ classes, but does use some of the standard Haskell type classes for its
+ built-in function, such as: \hs{Num} for numerical operations, \hs{Eq} for
+ the equality operators, and \hs{Ord} for the comparison/order operators.
\subsection{Higher-order functions \& values}
Another powerful abstraction mechanism in functional languages, is
value and be passed around, even as the argument of another
function. The following example should clarify this concept:
+%format not = "\mathit{not}"
\begin{code}
negateVector xs = map not xs
\end{code}
expression, that adds one to every element of a vector:
\begin{code}
- map (+ 1) xs
+ map (add 1) xs
\end{code}
- Here, the expression \hs{(+ 1)} is the partial application of the
- plus operator to the value \hs{1}, which is again a function that
+ Here, the expression \hs{(add 1)} is the partial application of the
+ addition function to the value \hs{1}, which is again a function that
adds one to its (next) argument. A lambda expression allows one to
introduce an anonymous function in any expression. Consider the following
expression, which again adds one to every element of a vector:
\begin{inparaenum}
\item given the same arguments twice, it should return the same value in
both cases, and
- \item when the function is called, it should not have observable
- side-effects.
+ \item that the function has no observable side-effects.
\end{inparaenum}
% This purity property is important for functional languages, since it
% enables all kinds of mathematical reasoning that could not be guaranteed
\label{img:mac-state}
\end{figure}
- The \hs{State} keyword indicates which arguments are part of the current
- state, and what part of the output is part of the updated state. This
- aspect will also be reflected in the type signature of the function.
- Abstracting the state of a circuit in this way makes it very explicit:
- which variables are part of the state is completely determined by the
- type signature. This approach to state is well suited to be used in
+ Note that the \hs{macS} function returns bot the new state and the value
+ of the output port. The \hs{State} keyword indicates which arguments are
+ part of the current state, and what part of the output is part of the
+ updated state. This aspect will also be reflected in the type signature of
+ the function. Abstracting the state of a circuit in this way makes it very
+ explicit: which variables are part of the state is completely determined
+ by the type signature. This approach to state is well suited to be used in
combination with the existing code and language features, such as all the
choice elements, as state values are just normal values. We can simulate
stateful descriptions using the recursive \hs{run} function:
first input value, \hs{i}. The result is the first output value, \hs{o},
and the updated state \hs{s'}. The next iteration of the \hs{run} function
is then called with the updated state, \hs{s'}, and the rest of the
- inputs, \hs{inps}. It is assumed that there is one input per clock cycle.
+ inputs, \hs{inps}. For the time being, and in the context of this paper,
+ It is assumed that there is one input per clock cycle.
Also note how the order of the input, output, and state in the \hs{run}
function corresponds with the order of the input, output and state of the
\hs{macS} function described earlier.
- As both the \hs{run} function, the hardware description, and the test
- inputs are plain Haskell, the complete simulation can be compiled to an
- executable binary by an optimizing Haskell compiler, or executed in an
+ As the \hs{run} function, the hardware description, and the test
+ inputs are also valid Haskell, the complete simulation can be compiled to
+ an executable binary by an optimizing Haskell compiler, or executed in an
Haskell interpreter. Both simulation paths are much faster than first
translating the description to \VHDL\ and then running a \VHDL\
- simulation, where the executable binary has an additional simulation speed
- bonus in case there is a large set of test inputs.
+ simulation.
-\section{\CLaSH\ compiler}
+\section{The \CLaSH\ compiler}
An important aspect in this research is the creation of the prototype
compiler, which allows us to translate descriptions made in the \CLaSH\
language as described in the previous section to synthesizable \VHDL, allowing
also provides a high level API to most of its internals. The availability of
this high-level API obviated the need to design many of the tedious parts of
the prototype compiler, such as the parser, semantic checker, and especially
-the type-checker. The parser, semantic checker, and type-checker together form
-the front-end of the prototype compiler pipeline, as depicted in
-\Cref{img:compilerpipeline}.
+the type-checker. These parts together form the front-end of the prototype compiler pipeline, as seen in \Cref{img:compilerpipeline}.
\begin{figure}
\centerline{\includegraphics{compilerpipeline.svg}}
\label{img:compilerpipeline}
\end{figure}
-The output of the \GHC\ front-end is the original Haskell description
-translated to \emph{Core}~\cite{Sulzmann2007}, which is smaller, typed,
-functional language that is relatively easier to process than the larger
-Haskell language. A description in \emph{Core} can still contain properties
-which have no direct translation to hardware, such as polymorphic types and
-function-valued arguments. Such a description needs to be transformed to a
-\emph{normal form}, which only contains properties that have a direct
-translation. The second stage of the compiler, the \emph{normalization} phase
-exhaustively applies a set of \emph{meaning-preserving} transformations on the
-\emph{Core} description until this description is in a \emph{normal form}.
-This set of transformations includes transformations typically found in
-reduction systems for lambda calculus~\cite{lambdacalculus}, such a
-$\beta$-reduction and $\eta$-expansion, but also includes self-defined
-transformations that are responsible for the reduction of higher-order
-functions to `regular' first-order functions.
+The output of the \GHC\ front-end consists of the translation of the original Haskell description in \emph{Core}~\cite{Sulzmann2007}, which is a smaller, typed, functional language. This \emph{Core} language is relatively easy to process compared to the larger Haskell language. A description in \emph{Core} can still contain elements which have no direct translation to hardware, such as polymorphic types and function-valued arguments. Such a description needs to be transformed to a \emph{normal form}, which only contains elements that have a direct translation. The second stage of the compiler, the \emph{normalization} phase, exhaustively applies a set of \emph{meaning-preserving} transformations on the \emph{Core} description until this description is in a \emph{normal form}. This set of transformations includes transformations typically found in reduction systems and lambda calculus~\cite{lambdacalculus}, such as $\beta$-reduction and $\eta$-expansion. It also includes self-defined transformations that are responsible for the reduction of higher-order functions to `regular' first-order functions.
The final step in the compiler pipeline is the translation to a \VHDL\
\emph{netlist}, which is a straightforward process due to resemblance of a
\VHDL\ resembles an actual netlist description and not idiomatic \VHDL.
\section{Use cases}
-
-\subsection{FIR Filter}
\label{sec:usecases}
+\subsection{FIR Filter}
As an example of a common hardware design where the use of higher-order
functions leads to a very natural description is a \acro{FIR} filter, which is
basically the dot-product of two vectors:
the \hs{foldl1} function is the result of the last application. It is obvious
that the \hs{zipWith (*)} function is pairwise multiplication and that the
\hs{foldl1 (+)} function is summation.
-
-Returning to the actual \acro{FIR} filter, we will slightly change the
-equation describing it, so as to make the translation to code more obvious and
-concise. What we do is change the definition of the vector of input samples
-and delay the computation by one sample. Instead of having the input sample
-received at time $t$ stored in $x_t$, $x_0$ now always stores the newest
-sample, and $x_i$ stores the $ith$ previous sample. This changes the equation
-to the following (note that this is completely equivalent to the original
-equation, just with a different definition of $x$ that will better suit the
-transformation to code):
-
-\begin{equation}
-y_t = \sum\nolimits_{i = 0}^{n - 1} {x_i \cdot h_i }
-\end{equation}
-
+% Returning to the actual \acro{FIR} filter, we will slightly change the
+% equation describing it, so as to make the translation to code more obvious and
+% concise. What we do is change the definition of the vector of input samples
+% and delay the computation by one sample. Instead of having the input sample
+% received at time $t$ stored in $x_t$, $x_0$ now always stores the newest
+% sample, and $x_i$ stores the $ith$ previous sample. This changes the equation
+% to the following (note that this is completely equivalent to the original
+% equation, just with a different definition of $x$ that will better suit the
+% transformation to code):
+%
+% \begin{equation}
+% y_t = \sum\nolimits_{i = 0}^{n - 1} {x_i \cdot h_i }
+% \end{equation}
The complete definition of the \acro{FIR} filter in code then becomes:
\begin{code}
-fir (State (xs,hs)) x = (State (x >> xs,hs), xs *+* hs)
+fir (State (xs,hs)) x =
+ (State (x >> xs,hs), (x +> xs) *+* hs)
\end{code}
-Where the vector \hs{hs} contains the \acro{FIR} coefficients and the vector
-\hs{xs} contains the latest input sample in front and older samples behind.
-The code for the shift (\hs{>>}) operator that adds the new input sample
-(\hs{x}) to the list of previous input samples (\hs{xs}) and removes the
-oldest sample is shown below:
+Where the vector \hs{xs} contains the previous input samples, the vector \hs{hs} contains the \acro{FIR} coefficients, and \hs{x} is the current input sample. The concatenate operator (\hs{+>}) creates a new vector by placing the current sample (\hs{x}) in front of the previous samples vector (\hs{xs}). The code for the shift (\hs{>>}) operator, that adds the new input sample (\hs{x}) to the list of previous input samples (\hs{xs}) and removes the oldest sample, is shown below:
\begin{code}
x >> xs = x +> init xs
\end{code}
-The \hs{init} function returns all but the last element of a vector, and the
-concatenate operator (\hs{+>}) adds a new element to the front of a vector.
+Where the \hs{init} function returns all but the last element of a vector.
The resulting netlist of a 4-taps \acro{FIR} filter, created by specializing
the vectors of the \acro{FIR} code to a length of 4, is depicted in
\Cref{img:4tapfir}.
\label{img:4tapfir}
\end{figure}
-\subsection{Higher order CPU}
+\subsection{Higher-order CPU}
+The following simple \acro{CPU} is an example of user-defined higher order
+functions and pattern matching. The \acro{CPU} consists of four function
+units, of which three have a fixed function and one can perform certain less
+common operations.
+
+The \acro{CPU} contains a number of data sources, represented by the
+horizontal wires in \Cref{img:highordcpu}. These data sources offer the
+previous outputs of each function units, along with the single data input the
+\acro{CPU} has and two fixed initialization values.
+
+Each of the function units has both its operands connected to all data
+sources, and can be programmed to select any data source for either
+operand. In addition, the leftmost function unit has an additional
+opcode input to select the operation it performs. The output of the rightmost
+function unit is also the output of the entire \acro{CPU}.
+
+Looking at the code, the function unit (\hs{fu}) is the most simple. It
+arranges the operand selection for the function unit. Note that it does not
+define the actual operation that takes place inside the function unit,
+but simply accepts the (higher-order) argument \hs{op} which is a function
+of two arguments that defines the operation.
\begin{code}
-type FuState = State Word
-fu :: (a -> a -> a)
- -> [a]:n
- -> (RangedWord n, RangedWord n)
- -> FuState
- -> (FuState, a)
-fu op inputs (addr1, addr2) (State out) =
- (State out', out)
+fu op inputs (addr1, addr2) = regIn
where
- in1 = inputs!addr1
- in2 = inputs!addr2
- out' = op in1 in2
+ in1 = inputs!addr1
+ in2 = inputs!addr2
+ regIn = op in1 in2
\end{code}
+The \hs{multiop} function defines the operation that takes place in the
+leftmost function unit. It is essentially a simple three operation \acro{ALU}
+that makes good use of pattern matching and guards in its description.
+The \hs{shift} function used here shifts its first operand by the number
+of bits indicated in the second operand, the \hs{xor} function produces
+the bitwise xor of its operands.
+
\begin{code}
-type CpuState = State [FuState]:4
-cpu :: Word
- -> [(RangedWord 7, RangedWord 7)]:4
- -> CpuState
- -> (CpuState, Word)
-cpu input addrs (State fuss) =
- (State fuss', out)
+data Opcode = Shift | Xor | Equal
+
+multiop :: Opcode -> Word -> Word -> Word
+multiop Shift a b = shift a b
+multiop Xor a b = xor a b
+multiop Equal a b | a == b = 1
+ | otherwise = 0
+\end{code}
+
+The \acro{CPU} function ties everything together. It applies the \hs{fu}
+function four times, to create a different function unit each time. The
+first application is interesting, because it does not just pass a
+function to \hs{fu}, but a partial application of \hs{multiop}. This
+shows how the first function unit effectively gets an extra input,
+compared to the others.
+
+The vector \hs{inputs} is the set of data sources, which is passed to
+each function unit as a set of possible operants. The \acro{CPU} also receives
+a vector of address pairs, which are used by each function unit to select
+their operand. The application of the function units to the \hs{inputs} and
+\hs{addrs} arguments seems quite repetitive and could be rewritten to use
+a combination of the \hs{map} and \hs{zipwith} functions instead.
+However, the prototype compiler does not currently support working with lists of functions, so a more explicit version of the code is given instead.
+
+\begin{code}
+type CpuState = State [Word | 4]
+
+cpu :: CpuState -> Word -> [(Index 6, Index 6) | 4]
+ -> Opcode -> (CpuState, Word)
+cpu (State s) input addrs opc = (State s', out)
where
- fures = [ fu const inputs!0 fuss!0
- , fu (+) inputs!1 fuss!1
- , fu (-) inputs!2 fuss!2
- , fu (*) inputs!3 fuss!3
- ]
- (fuss', outputs) = unzip fures
- inputs = 0 +> 1 +> input +> outputs
- out = head outputs
+ s' = [ fu (multiop opc) inputs (addrs!0)
+ , fu add inputs (addrs!1)
+ , fu sub inputs (addrs!2)
+ , fu mul inputs (addrs!3)
+ ]
+ inputs = 0 +> (1 +> (input +> s))
+ out = head s'
\end{code}
+\begin{figure}
+\centerline{\includegraphics{highordcpu.svg}}
+\caption{CPU with higher-order Function Units}
+\label{img:highordcpu}
+\end{figure}
+
+This is still a simple example, but it could form the basis
+of an actual design, in which the same techniques can be reused.
+
\section{Related work}
+This section describes the features of existing (functional) hardware
+description languages and highlights the advantages that this research has
+over existing work.
+
Many functional hardware description languages have been developed over the
years. Early work includes such languages as $\mu$\acro{FP}~\cite{muFP}, an
extension of Backus' \acro{FP} language to synchronous streams, designed
functional language \acro{ML}, and has support for polymorphic types and
higher-order functions. Published work suggests that there is no direct
simulation support for \acro{HML}, but that a description in \acro{HML} has to
-be translated to \VHDL\ and that the translated description can than be
+be translated to \VHDL\ and that the translated description can then be
simulated in a \VHDL\ simulator. Also not all of the mentioned language
features of \acro{HML} could be translated to hardware. The \CLaSH\ compiler
on the other hand can correctly translate all of the language constructs
mentioned in this paper to a netlist format.
-Like this work, many functional hardware description languages have some sort
-of foundation in the functional programming language Haskell.
-Hawk~\cite{Hawk1} uses Haskell to describe system-level executable
+Like the work presented in this paper, many functional hardware description languages have some sort of foundation in the functional programming language Haskell. Hawk~\cite{Hawk1} uses Haskell to describe system-level executable
specifications used to model the behavior of superscalar microprocessors. Hawk
-specifications can be simulated, but there seems to be no support for
-automated circuit synthesis.
+specifications can be simulated; to the best knowledge of the authors there is however no support for automated circuit synthesis.
The ForSyDe~\cite{ForSyDe2} system uses Haskell to specify abstract system
models, which can (manually) be transformed into an implementation model using
elements of Haskell, such as choice, can be used to guide the circuit
generation. If a developer wants to insert a choice element inside an actual
circuit he will have to explicitly instantiate a multiplexer-like component.
-
In this respect \CLaSH\ differs from Lava, in that all the choice elements,
such as case-statements and pattern matching, are synthesized to choice
elements in the eventual circuit. As such, richer control structures can both
-be specified and synthesized in \CLaSH\ compared to any of the languages
-mentioned in this section.
+be specified and synthesized in \CLaSH\ compared to any of the embedded
+languages such as Hawk, ForSyDe and Lava.
The merits of polymorphic typing, combined with higher-order functions, are
now also recognized in the `main-stream' hardware description languages,
-exemplified by the new \VHDL-2008 standard~\cite{VHDL2008}. \VHDL-2008 support for generics has been extended to types, allowing a developer to describe
-polymorphic components. Note that those types still require an explicit
-generic map, whereas types can be automatically inferred in \CLaSH.
+exemplified by the new \VHDL-2008 standard~\cite{VHDL2008}. \VHDL-2008 support
+for generics has been extended to types and subprograms, allowing a developer
+to describe components with polymorphic ports and function-valued arguments.
+Note that the types and subprograms still require an explicit generic map,
+whereas types can be automatically inferred, and function-values can be
+automatically propagated by the \CLaSH\ compiler. There are also no (generally
+available) \VHDL\ synthesis tools that currently support the \VHDL-2008
+standard, and thus the synthesis of polymorphic types and function-valued
+arguments.
% Wired~\cite{Wired},, T-Ruby~\cite{T-Ruby}, Hydra~\cite{Hydra}.
%
\section{Conclusion}
-The conclusion goes here.
-
-
-
+This research demonstrates once more that functional languages are well suited
+for hardware descriptions: function applications provide an elegant notation
+for component instantiation. Where this research goes beyond the existing
+(functional) hardware descriptions languages is the inclusion of various
+choice elements, such as patter matching, that are well suited to describe the
+conditional assignments in control-oriented hardware. Besides being able to
+translate these basic constructs to synthesizable \VHDL, the prototype
+compiler can also correctly translate descriptions that contain both
+polymorphic types and function-valued arguments.
+
+Where recent functional hardware description languages have mostly opted to
+embed themselves in an existing functional language, this research features a
+`true' compiler. As a result there is a clear distinction between compile-time
+and run-time, which allows a myriad of choice constructs to be part of the
+actual circuit description; a feature the embedded hardware description
+languages do not offer.
+
+\section{Future Work}
+The choice of describing state explicitly as extra arguments and results can
+be seen as a mixed blessing. Even though the description that use state are
+usually very clear, one finds that dealing with unpacking, passing, receiving
+and repacking can become tedious and even error-prone, especially in the case
+of sub-states. Removing this boilerplate, or finding a more suitable
+abstraction mechanism would make \CLaSH\ easier to use.
+
+The transformations in normalization phase of the prototype compiler were
+developed in an ad-hoc manner, which makes the existence of many desirable
+properties unclear. Such properties include whether the complete set of
+transformations will always lead to a normal form or if the normalization
+process always terminates. Though various use cases suggests that these
+properties usually hold, they have not been formally proven. A systematic
+approach to defining the set of transformations allows one to proof that the
+earlier mentioned properties do indeed exist.
% conference papers do not normally have an appendix
% use section* for acknowledgement
-\section*{Acknowledgment}
-
-
-The authors would like to thank...
-
-
-
-
+% \section*{Acknowledgment}
+%
+% The authors would like to thank...
% trigger a \newpage just before the given reference
% number - used to balance the columns on the last page
% adjust value as needed - may need to be readjusted if
% the document is modified later
-%\IEEEtriggeratref{8}
+% \IEEEtriggeratref{14}
% The "triggered" command can be changed if desired:
%\IEEEtriggercmd{\enlargethispage{-5in}}
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