Improve / shorten the section on types.

[matthijs/master-project/dsd-paper.git] / cλash.lhs

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\title{\CLaSH: Structural Descriptions \\ of Synchronous Hardware using Haskell}


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\IEEEauthorblockA{University of Twente, Department of EEMCS\\
P.O. Box 217, 7500 AE, Enschede, The Netherlands\\
c.p.r.baaij@utwente.nl, matthijs@stdin.nl}}
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\section{Introduction}
Hardware description languages has allowed the productivity of hardware 
engineers to keep pace with the development of chip technology. Standard 
Hardware description languages, like \VHDL\ and Verilog, allowed an engineer 
to describe circuits using a programming language. These standard languages 
are very good at describing detailed hardware properties such as timing 
behavior, but are generally cumbersome in expressing higher-level 
abstractions. These languages also tend to have a complex syntax and a lack of 
formal semantics. To overcome these complexities, and raise the abstraction 
level, a great number of approaches based on functional languages has been 
proposed \cite{T-Ruby,Hydra,HML2,Hawk1,Lava,ForSyDe1,Wired,reFLect}. The idea 
of using functional languages started in the early 1980s \cite{Cardelli1981,
muFP,DAISY,FHDL}, a time which also saw the birth of the currently popular 
hardware description languages such as \VHDL.

What gives functional languages as hardware description languages their merits 
is the fact that basic combinatorial circuits are equivalent to mathematical 
function, and that functional languages lend themselves very well to describe 
and compose these mathematical functions.
\section{Hardware description in Haskell}

  \subsection{Function application}
    The basic syntactic elements of a functional program are functions
    and function application. These have a single obvious \VHDL\
    translation: each top level function becomes a hardware component,
    where each argument is an input port and the result value is the
    (single) output port. This output port can have a complex type (such
    as a tuple), so having just a single output port does not create a
    limitation.

    Each function application in turn becomes component instantiation.
    Here, the result of each argument expression is assigned to a
    signal, which is mapped to the corresponding input port. The output
    port of the function is also mapped to a signal, which is used as
    the result of the application itself.

    Since every top level function generates its own component, the
    hierarchy of of function calls is reflected in the final \VHDL\
    output as well, creating a hierarchical \VHDL\ description of the
    hardware.  This separation in different components makes the
    resulting \VHDL\ output easier to read and debug.

    Example that defines the \texttt{mac} function by applying the
    \texttt{add} and \texttt{mul} functions to calculate $a * b + c$:

\begin{verbatim}
mac a b c = add (mul a b) c
\end{verbatim}

    TODO: Pretty picture

  \subsection{Choices }
    Although describing components and connections allows describing a
    lot of hardware designs already, there is an obvious thing missing:
    choice. We need some way to be able to choose between values based
    on another value.  In Haskell, choice is achieved by \hs{case}
    expressions, \hs{if} expressions, pattern matching and guards.

    The easiest of these are of course case expressions (and \hs{if}
    expressions, which can be very directly translated to \hs{case}
    expressions). A \hs{case} expression can in turn simply be
    translated to a conditional assignment in \VHDL, where the
    conditions use equality comparisons against the constructors in the
    \hs{case} expressions.

    A slightly more complex (but very powerful) form of choice is
    pattern matching. A function can be defined in multiple clauses,
    where each clause specifies a pattern. When the arguments match the
    pattern, the corresponding clause will be used.

    A pattern match (with optional guards) can also be implemented using
    conditional assignments in \VHDL, where the condition is the logical
    and of comparison results of each part of the pattern as well as the
    guard.

    Contrived example that sums two values when they are equal or
    non-equal (depending on the predicate given) and returns 0
    otherwise. This shows three implementations, one using and if
    expression, one using only case expressions and one using pattern
    matching and guards.

\begin{verbatim}
sumif pred a b = if pred == Eq && a == b || pred == Neq && a != b
                 then a + b
                 else 0
\end{verbatim}

\begin{verbatim}
sumif pred a b = case pred of
  Eq -> case a == b of
    True -> a + b
    False -> 0
  Neq -> case a != b of
    True -> a + b
    False -> 0
\end{verbatim}

\begin{verbatim}
sumif Eq a b | a == b = a + b
sumif Neq a b | a != b = a + b
sumif _ _ _ = 0
\end{verbatim}

  TODO: Pretty picture

  \subsection{Types}
    Translation of two most basic functional concepts has been
    discussed: function application and choice. Before looking further
    into less obvious concepts like higher-order expressions and
    polymorphism, the possible types that can be used in hardware
    descriptions will be discussed.

    Some way is needed to translate every value used to its hardware
    equivalents. In particular, this means a hardware equivalent for
    every \emph{type} used in a hardware description is needed.

    The following types are \emph{built-in}, meaning that their hardware
    translation is fixed into the \CLaSH compiler. A designer can also
    define his own types, which will be translated into hardware types
    using translation rules that are discussed later on.

  \subsection{Built-in types}
    \begin{xlist}
      \item[\hs{Bit}]
        This is the most basic type available. It can have two values:
        \hs{Low} and \hs{High}. It is mapped directly onto the
        \texttt{std\_logic} \VHDL\ type. 
      \item[\hs{Bool}]
        This is a basic logic type. It can have two values: \hs{True}
        and \hs{False}. It is translated to \texttt{std\_logic} exactly
        like the \hs{Bit} type (where a value of \hs{True} corresponds
        to a value of \hs{High}). Supporting the Bool type is
        particularly useful to support \hs{if ... then ... else ...}
        expressions, which always have a \hs{Bool} value for the
        condition.
      \item[\hs{SizedWord}, \hs{SizedInt}]
        These are types to represent integers. A \hs{SizedWord} is unsigned,
        while a \hs{SizedInt} is signed. These types are parametrized by a
        length type, so you can define an unsigned word of 32 bits wide as
        follows:

\begin{verbatim}
type Word32 = SizedWord D32
\end{verbatim}

        Here, a type synonym \hs{Word32} is defined that is equal to the
        \hs{SizedWord} type constructor applied to the type \hs{D32}. \hs{D32}
        is the \emph{type level representation} of the decimal number 32,
        making the \hs{Word32} type a 32-bit unsigned word.

        These types are translated to the \VHDL\ \texttt{unsigned} and
        \texttt{signed} respectively.
      \item[\hs{Vector}]
        This is a vector type, that can contain elements of any other type and
        has a fixed length.

        The \hs{Vector} type constructor takes two type arguments: the length
        of the vector and the type of the elements contained in it. The state
        type of an 8 element register bank would then for example be:

\begin{verbatim}
type RegisterState = Vector D8 Word32
\end{verbatim}

        Here, a type synonym \hs{RegisterState} is defined that is equal to
        the \hs{Vector} type constructor applied to the types \hs{D8} (The type
        level representation of the decimal number 8) and \hs{Word32} (The 32
        bit word type as defined above). In other words, the
        \hs{RegisterState} type is a vector of 8 32-bit words.

        A fixed size vector is translated to a \VHDL\ array type.
      \item[\hs{RangedWord}]
        This is another type to describe integers, but unlike the previous
        two it has no specific bit-width, but an upper bound. This means that
        its range is not limited to powers of two, but can be any number.
        A \hs{RangedWord} only has an upper bound, its lower bound is
        implicitly zero.

        The main purpose of the \hs{RangedWord} type is to be used as an
        index to a \hs{Vector}.

        TODO: Perhaps remove this example?

        To define an index for the 8 element vector above, we would do:

\begin{verbatim}
type RegisterIndex = RangedWord D7
\end{verbatim}

        Here, a type synonym \hs{RegisterIndex} is defined that is equal to
        the \hs{RangedWord} type constructor applied to the type \hs{D7}. In
        other words, this defines an unsigned word with values from
        0 to 7 (inclusive). This word can be be used to index the
        8 element vector \hs{RegisterState} above.

        This type is translated to the \texttt{unsigned} \VHDL type.
    \end{xlist}

  \subsection{User-defined types}
    There are three ways to define new types in Haskell: algebraic
    data-types with the \hs{data} keyword, type synonyms with the \hs{type}
    keyword and type renamings with the \hs{newtype} keyword. \GHC\
    offers a few more advanced ways to introduce types (type families,
    existential typing, {\small{GADT}}s, etc.) which are not standard
    Haskell. These are not currently supported.

    Only an algebraic datatype declaration actually introduces a
    completely new type, for which we provide the \VHDL\ translation
    below. Type synonyms and renamings only define new names for
    existing types (where synonyms are completely interchangeable and
    renamings need explicit conversion). Therefore, these do not need
    any particular \VHDL\ translation, a synonym or renamed type will
    just use the same representation as the original type. The
    distinction between a renaming and a synonym does no longer matter
    in hardware and can be disregarded in the generated \VHDL.

    For algebraic types, we can make the following distinction: 

    \begin{xlist}
      \item[\bf{Single constructor}]
        Algebraic datatypes with a single constructor with one or more
        fields, are essentially a way to pack a few values together in a
        record-like structure.

        An example of such a type is the following pair of integers:

\begin{verbatim}
data IntPair = IntPair Int Int
\end{verbatim}

        Haskell's builtin tuple types are also defined as single
        constructor algebraic types and are translated according to this
        rule by the \CLaSH compiler.

        These types are translated to \VHDL\ record types, with one field for
        every field in the constructor.
      \item[\bf{No fields}]
        Algebraic datatypes with multiple constructors, but without any
        fields are essentially a way to get an enumeration-like type
        containing alternatives.

        Note that Haskell's \hs{Bool} type is also defined as an
        enumeration type, but we have a fixed translation for that.

        These types are translated to \VHDL\ enumerations, with one value for
        each constructor. This allows references to these constructors to be
        translated to the corresponding enumeration value.
      \item[\bf{Multiple constructors with fields}]
        Algebraic datatypes with multiple constructors, where at least
        one of these constructors has one or more fields are not
        currently supported.
      \end{xlist}


\section{\CLaSH\ prototype}

foo\par bar

\section{Related work}
Many functional hardware description languages have been developed over the 
years. Early work includes such languages as \textsc{$\mu$fp}~\cite{muFP}, an 
extension of Backus' \textsc{fp} language to synchronous streams, designed 
particularly for describing and reasoning about regular circuits. The 
Ruby~\cite{Ruby} language uses relations, instead of functions, to describe 
circuits, and has a particular focus on layout. \textsc{hml}~\cite{HML2} is a 
hardware modeling language based on the strict functional language 
\textsc{ml}, and has support for polymorphic types and higher-order functions. 
Published work suggests that there is no direct simulation support for 
\textsc{hml}, and that the translation to \VHDL\ is only partial.

Like this work, many functional hardware description languages have some sort 
of foundation in the functional programming language Haskell. 
Hawk~\cite{Hawk1} uses Haskell to describe system-level executable 
specifications used to model the behavior of superscalar microprocessors. Hawk 
specifications can be simulated, but there seems to be no support for 
automated circuit synthesis. The ForSyDe~\cite{ForSyDe2} system uses Haskell 
to specify abstract system models, which can (manually) be transformed into an 
implementation model using semantic preserving transformations. ForSyDe has 
several simulation and synthesis backends, though synthesis is restricted to 
the synchronous subset of the ForSyDe language.

Lava~\cite{Lava} is a hardware description language that focuses on the 
structural representation of hardware. Besides support for simulation and 
circuit synthesis, Lava descriptions can be interfaced with formal method 
tools for formal verification. Lava descriptions are actually circuit 
generators when viewed from a synthesis viewpoint, in that the language 
elements of Haskell, such as choice, can be used to guide the circuit 
generation. If a developer wants to insert a choice element inside an actual 
circuit he will have to specify this explicitly as a component. In this 
respect \CLaSH\ differs from Lava, in that all the choice elements, such as 
case-statements and patter matching, are synthesized to choice elements in the 
eventual circuit. As such, richer control structures can both be specified and 
synthesized in \CLaSH\ compared to any of the languages mentioned in this 
section.

The merits of polymorphic typing, combined with higher-order functions, are 
now also recognized in the `main-stream' hardware description languages, 
exemplified by the new \VHDL\ 2008 standard~\cite{VHDL2008}. \VHDL-2008 has 
support to specify types as generics, thus allowing a developer to describe 
polymorphic components. Note that those types still require an explicit 
generic map, whereas type-inference and type-specialization are implicit in 
\CLaSH.

Wired~\cite{Wired},, T-Ruby~\cite{T-Ruby}, Hydra~\cite{Hydra}. 

A functional language designed specifically for hardware design is 
$re{\mathit{FL}}^{ect}$~\cite{reFLect}, which draws experience from earlier 
language called \textsc{fl}~\cite{FL} to la

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\section{Conclusion}
The conclusion goes here.




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The authors would like to thank...





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