From f69e59a92472c3a827ac25b52ab5d70895e19b7e Mon Sep 17 00:00:00 2001 From: christiaanb Date: Wed, 23 Jun 2010 12:05:35 +0200 Subject: [PATCH] rotate alternatives of a case-statement if there is a default case --- clash/CLasH/VHDL/Generate.hs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/clash/CLasH/VHDL/Generate.hs b/clash/CLasH/VHDL/Generate.hs index 191ae9c..06bc265 100644 --- a/clash/CLasH/VHDL/Generate.hs +++ b/clash/CLasH/VHDL/Generate.hs @@ -311,7 +311,11 @@ mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) _ _ alts)) = do -- alternatives. let cond_exprs = map (\x -> cmp AST.:=: x) altcons -- Rotate expressions to the left, so that the expression related to the default case is the last - exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) ((tail alts) ++ [head alts]) + let alts' = case alts of + ((CoreSyn.DEFAULT,_,_):_) -> ((tail alts) ++ [head alts]) + otherwise -> alts + + exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) alts' --((tail alts) ++ [head alts]) return ([mkAltsAssign (Left bndr) cond_exprs exprs], []) mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement does not have a simple variable as scrutinee" -- 2.30.2