From d12fa2e2d090cb0792e1d94413787ee20946c655 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Thu, 6 Aug 2009 12:06:32 +0200 Subject: [PATCH] Remove the unused "stateful" argument fomr makeVHDL*. State will be explicitely specified in the Haskell sources, so no reason anymore to pass the statefulness of a function around. --- "c\316\273ash/CLasH/Translator.hs" | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git "a/c\316\273ash/CLasH/Translator.hs" "b/c\316\273ash/CLasH/Translator.hs" index c4daf04..b61f5f9 100644 --- "a/c\316\273ash/CLasH/Translator.hs" +++ "b/c\316\273ash/CLasH/Translator.hs" @@ -42,10 +42,9 @@ makeVHDLStrings :: -> String -- ^ The TopEntity -> String -- ^ The InitState -> String -- ^ The TestInput - -> Bool -- ^ Is it stateful? (in case InitState is empty) -> IO () -makeVHDLStrings libdir filenames topentity initstate testinput stateful = do - makeVHDL libdir filenames finder stateful +makeVHDLStrings libdir filenames topentity initstate testinput = do + makeVHDL libdir filenames finder where finder = findSpec (hasVarName topentity) (hasVarName initstate) @@ -56,10 +55,9 @@ makeVHDLStrings libdir filenames topentity initstate testinput stateful = do makeVHDLAnnotations :: FilePath -- ^ The GHC Library Dir -> [FilePath] -- ^ The FileNames - -> Bool -- ^ Is it stateful? (in case InitState is not specified) -> IO () -makeVHDLAnnotations libdir filenames stateful = do - makeVHDL libdir filenames finder stateful +makeVHDLAnnotations libdir filenames = do + makeVHDL libdir filenames finder where finder = findSpec (hasCLasHAnnotation isTopEntity) (hasCLasHAnnotation isInitState) @@ -71,13 +69,12 @@ makeVHDL :: FilePath -- ^ The GHC Library Dir -> [FilePath] -- ^ The Filenames -> Finder - -> Bool -- ^ Indicates if it is meant to be stateful -> IO () -makeVHDL libdir filenames finder stateful = do +makeVHDL libdir filenames finder = do -- Load the modules (cores, env, specs) <- loadModules libdir filenames (Just finder) -- Translate to VHDL - vhdl <- moduleToVHDL env cores specs stateful + vhdl <- moduleToVHDL env cores specs -- Write VHDL to file. Just use the first entity for the name let top_entity = (\(t, _, _) -> t) $ head specs let dir = "./vhdl/" ++ (show top_entity) ++ "/" @@ -85,16 +82,13 @@ makeVHDL libdir filenames finder stateful = do mapM (writeVHDL dir) vhdl return () --- | Translate the binds with the given names from the given core module to --- VHDL. The Bool in the tuple makes the function stateful (True) or --- stateless (False). +-- | Translate the specified entities in the given modules to VHDL. moduleToVHDL :: HscTypes.HscEnv -- ^ The GHC Environment -> [HscTypes.CoreModule] -- ^ The Core Modules -> [EntitySpec] -- ^ The entities to generate - -> Bool -- ^ Is it stateful (in case InitState is not specified) -> IO [(AST.VHDLId, AST.DesignFile)] -moduleToVHDL env cores specs stateful = do +moduleToVHDL env cores specs = do vhdl <- runTranslatorSession env $ do let all_bindings = concat (map (\x -> CoreSyn.flattenBinds (HscTypes.cm_binds x)) cores) -- Store the bindings we loaded -- 2.30.2