From 374a42ba3cf333ae53fa1d992620d25286641ae2 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Thu, 6 Aug 2009 17:45:56 +0200 Subject: [PATCH] Put mkAssocElems in the TranslatorSession. --- "c\316\273ash/CLasH/VHDL/Generate.hs" | 2 +- "c\316\273ash/CLasH/VHDL/Testbench.hs" | 3 +-- "c\316\273ash/CLasH/VHDL/VHDLTools.hs" | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index 5698ef8..0b2cf04 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -778,7 +778,7 @@ genApplication dst f args = do -- TODO: Using show here isn't really pretty, but we'll need some -- unique-ish value... let label = "comp_ins_" ++ (either show prettyShow) dst - let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature + portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature return ([mkComponentInst label entity_id portmaps], [f]) False -> do -- Not a top level binder, so this must be a local variable reference. diff --git "a/c\316\273ash/CLasH/VHDL/Testbench.hs" "b/c\316\273ash/CLasH/VHDL/Testbench.hs" index 76fc073..b7f281b 100644 --- "a/c\316\273ash/CLasH/VHDL/Testbench.hs" +++ "b/c\316\273ash/CLasH/VHDL/Testbench.hs" @@ -1,4 +1,3 @@ --- -- Functions to create a VHDL testbench from a list of test input. -- module CLasH.VHDL.Testbench where @@ -75,7 +74,7 @@ createTestbenchArch mCycles stimuli top testent= do [AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"), AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")] let oDecs = AST.SigDec (fst oIface) (snd oIface) Nothing - let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature + portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature let mIns = mkComponentInst "totest" entId portmaps (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds) let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==: diff --git "a/c\316\273ash/CLasH/VHDL/VHDLTools.hs" "b/c\316\273ash/CLasH/VHDL/VHDLTools.hs" index a8fe239..bd16acd 100644 --- "a/c\316\273ash/CLasH/VHDL/VHDLTools.hs" +++ "b/c\316\273ash/CLasH/VHDL/VHDLTools.hs" @@ -85,10 +85,10 @@ mkAssocElems :: [AST.Expr] -- ^ The argument that are applied to function -> AST.VHDLName -- ^ The binder in which to store the result -> Entity -- ^ The entity to map against. - -> [AST.AssocElem] -- ^ The resulting port maps + -> TranslatorSession [AST.AssocElem] -- ^ The resulting port maps mkAssocElems args res entity = -- Create the actual AssocElems - zipWith mkAssocElem ports sigs + return $ zipWith mkAssocElem ports sigs where -- Turn the ports and signals from a map into a flat list. This works, -- since the maps must have an identical form by definition. TODO: Check -- 2.30.2