From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Sat, 29 Aug 2009 16:11:15 +0000 (+0200)
Subject: Use boolean as write enable signal
X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fc%CE%BBash.git;a=commitdiff_plain;h=17a28ae8c5e86427124022ec074305cacad83556

Use boolean as write enable signal
---

diff --git "a/c\316\273ash/CLasH/HardwareTypes.hs" "b/c\316\273ash/CLasH/HardwareTypes.hs"
index cff5c88..e6e84fd 100644
--- "a/c\316\273ash/CLasH/HardwareTypes.hs"
+++ "b/c\316\273ash/CLasH/HardwareTypes.hs"
@@ -84,13 +84,14 @@ blockRAM ::
   a ->
   RangedWord s ->
   RangedWord s ->
-  Bit -> 
+  Bool -> 
   ((MemState s a), a )
 blockRAM (State mem) data_in rdaddr wraddr wrenable = 
   ((State mem'), data_out)
   where
     data_out  = mem!rdaddr
     -- Only write data_in to memory if write is enabled
-    mem' = case wrenable of
-      Low   ->  mem
-      High  ->  replace mem wraddr data_in
+    mem' =  if wrenable then
+              replace mem wraddr data_in
+            else
+              mem
diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index 5881007..ecaad62 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -881,7 +881,7 @@ genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
         wform       = AST.Wform [AST.WformElem data_in Nothing]
         ramassign      = AST.SigAssign ramloc wform
         rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
-        statement   = AST.IfSm (AST.And rising_edge_clk (wrenable AST.:=: AST.PrimLit "'1'")) [ramassign] [] Nothing
+        statement   = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
 
 -----------------------------------------------------------------------------
 -- Function to generate VHDL for applications