Don't generate a signal for the output port.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 09:49:57 +0000 (11:49 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 09:49:57 +0000 (11:49 +0200)
commit01012813997b2f30e4c1df4d43c1e7e5de0135a8
tree86dfad17ba115bf1b7a605a2e4fdcabe375c1533
parentcccb87b1cdff39f45148b525bd8e426b6bf667ad
Don't generate a signal for the output port.
VHDL.hs