X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fc%CE%BBash.git;a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FTranslator.hs;h=a9bb9fa4cfed041f1ba5b69d6b82fe4b75857689;hp=79bd8d2e74ab9d7a97ace0d21849810f145add6d;hb=0223b461a043e42d3fc5442904b73ce0bd537472;hpb=f57f2e77081ccb768521d189d60d1fba645eab2a diff --git "a/c\316\273ash/CLasH/Translator.hs" "b/c\316\273ash/CLasH/Translator.hs" index 79bd8d2..a9bb9fa 100644 --- "a/c\316\273ash/CLasH/Translator.hs" +++ "b/c\316\273ash/CLasH/Translator.hs" @@ -94,7 +94,7 @@ moduleToVHDL :: -> [EntitySpec] -- ^ The entities to generate -> IO [(AST.VHDLId, AST.DesignFile)] moduleToVHDL env cores specs = do - vhdl <- runTranslatorSession env $ do + (vhdl, count) <- runTranslatorSession env $ do let all_bindings = concatMap (\x -> CoreSyn.flattenBinds (HscTypes.cm_binds x)) cores -- Store the bindings we loaded tsBindings %= Map.fromList all_bindings @@ -102,10 +102,13 @@ moduleToVHDL env cores specs = do tsInitStates %= Map.fromList all_initstates test_binds <- catMaybesM $ Monad.mapM mkTest specs let topbinds = Maybe.catMaybes $ map (\(top, _, _) -> top) specs - case topbinds of + vhdl <- case topbinds of [] -> error "Could not find top entity requested" tops -> createDesignFiles (tops ++ test_binds) + count <- get tsTransformCounter + return (vhdl, count) mapM_ (putStr . render . Ppr.ppr . snd) vhdl + putStr $ "Total number of transformations applied: " ++ (show count) ++ "\n" return vhdl where mkTest :: EntitySpec -> TranslatorSession (Maybe CoreSyn.CoreBndr) @@ -127,7 +130,7 @@ runTranslatorSession env session = do -- a unique supply anywhere. uniqSupply <- UniqSupply.mkSplitUniqSupply 'z' let init_typestate = TypeState builtin_types [] Map.empty Map.empty env - let init_state = TranslatorState uniqSupply init_typestate Map.empty Map.empty 0 Map.empty Map.empty Map.empty + let init_state = TranslatorState uniqSupply init_typestate Map.empty Map.empty 0 Map.empty Map.empty Map.empty 0 return $ State.evalState session init_state -- | Prepares the directory for writing VHDL files. This means creating the