X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fc%CE%BBash.git;a=blobdiff_plain;f=c%CE%BBash%2FCLasH%2FTranslator.hs;h=6177dabaca9fc069374da39caf6995e4f8c69ba7;hp=8f2c7dc98d2b05e7bc7bd2ea6baa71a95cb7ac9f;hb=e1ef152dc63f28dddce2de4950ec739c79c8d18f;hpb=e0e788e2f29dd85895c511e294718d440a42061d diff --git "a/c\316\273ash/CLasH/Translator.hs" "b/c\316\273ash/CLasH/Translator.hs" index 8f2c7dc..6177dab 100644 --- "a/c\316\273ash/CLasH/Translator.hs" +++ "b/c\316\273ash/CLasH/Translator.hs" @@ -1,6 +1,6 @@ module CLasH.Translator - ( makeVHDLStrings - , makeVHDLAnnotations + ( + makeVHDLAnnotations ) where -- Standard Modules @@ -8,106 +8,113 @@ import qualified System.Directory as Directory import qualified Maybe import qualified Monad import qualified System.FilePath as FilePath +import qualified Control.Monad.Trans.State as State import Text.PrettyPrint.HughesPJ (render) +import Data.Accessor.Monad.Trans.State +import qualified Data.Map as Map +import qualified Data.Time.Clock as Clock +import Debug.Trace -- GHC API import qualified CoreSyn -import qualified GHC import qualified HscTypes import qualified UniqSupply -- VHDL Imports import qualified Language.VHDL.AST as AST -import qualified Language.VHDL.FileIO +import qualified Language.VHDL.FileIO as FileIO import qualified Language.VHDL.Ppr as Ppr -- Local Imports -import CLasH.Normalize +import CLasH.Translator.TranslatorTypes import CLasH.Translator.Annotations -import CLasH.Utils.Core.CoreTools +import CLasH.Utils import CLasH.Utils.GhcTools import CLasH.VHDL - --- | Turn Haskell to VHDL, Usings Strings to indicate the Top Entity, Initial --- State and Test Inputs. -makeVHDLStrings :: - FilePath -- ^ The GHC Library Dir - -> [FilePath] -- ^ The FileNames - -> String -- ^ The TopEntity - -> String -- ^ The InitState - -> String -- ^ The TestInput - -> Bool -- ^ Is it stateful? (in case InitState is empty) - -> IO () -makeVHDLStrings libdir filenames topentity initstate testinput stateful = do - makeVHDL libdir filenames findTopEntity findInitState findTestInput stateful - where - findTopEntity = findBind (hasVarName topentity) - findInitState = findBind (hasVarName initstate) - findTestInput = findExpr (hasVarName testinput) +import CLasH.VHDL.VHDLTools +import CLasH.VHDL.Testbench -- | Turn Haskell to VHDL, Using the Annotations for Top Entity, Initial State -- and Test Inputs found in the Files. makeVHDLAnnotations :: FilePath -- ^ The GHC Library Dir -> [FilePath] -- ^ The FileNames - -> Bool -- ^ Is it stateful? (in case InitState is not specified) -> IO () -makeVHDLAnnotations libdir filenames stateful = do - makeVHDL libdir filenames findTopEntity findInitState findTestInput stateful +makeVHDLAnnotations libdir filenames = + makeVHDL libdir filenames finder where - findTopEntity = findBind (hasCLasHAnnotation isTopEntity) - findInitState = findBind (hasCLasHAnnotation isInitState) - findTestInput = findExpr (hasCLasHAnnotation isTestInput) + finder = findSpec (hasCLasHAnnotation isTopEntity) + (hasCLasHAnnotation isInitState) + (isCLasHAnnotation isInitState) + (hasCLasHAnnotation isTestInput) -- | Turn Haskell to VHDL, using the given finder functions to find the Top -- Entity, Initial State and Test Inputs in the Haskell Files. makeVHDL :: FilePath -- ^ The GHC Library Dir -> [FilePath] -- ^ The Filenames - -> (HscTypes.CoreModule -> GHC.Ghc (Maybe CoreSyn.CoreBndr)) -- ^ The Top Entity Finder - -> (HscTypes.CoreModule -> GHC.Ghc (Maybe CoreSyn.CoreBndr)) -- ^ The Init State Finder - -> (HscTypes.CoreModule -> GHC.Ghc (Maybe CoreSyn.CoreExpr)) -- ^ The Test Input Finder - -> Bool -- ^ Indicates if it is meant to be stateful + -> Finder -> IO () -makeVHDL libdir filenames topEntFinder initStateFinder testInputFinder stateful = do +makeVHDL libdir filenames finder = do + start <- Clock.getCurrentTime -- Load the modules - (cores, top, init, test, env) <- loadModules libdir filenames topEntFinder initStateFinder testInputFinder + (cores, env, specs) <- loadModules libdir filenames (Just finder) -- Translate to VHDL - vhdl <- moduleToVHDL env cores top init test stateful - -- Write VHDL to file - let top_entity = Maybe.fromJust $ head top + vhdl <- moduleToVHDL env cores specs + -- Write VHDL to file. Just use the first entity for the name + let top_entity = head $ Maybe.catMaybes $ map (\(t, _, _) -> t) specs let dir = "./vhdl/" ++ (show top_entity) ++ "/" prepareDir dir - mapM (writeVHDL dir) vhdl - return () + mapM_ (writeVHDL dir) vhdl + end <- Clock.getCurrentTime + trace ("\nTotal compilation took " ++ show (Clock.diffUTCTime end start)) $ + return () --- | Translate the binds with the given names from the given core module to --- VHDL. The Bool in the tuple makes the function stateful (True) or --- stateless (False). +-- | Translate the specified entities in the given modules to VHDL. moduleToVHDL :: HscTypes.HscEnv -- ^ The GHC Environment -> [HscTypes.CoreModule] -- ^ The Core Modules - -> [Maybe CoreSyn.CoreBndr] -- ^ The TopEntity - -> [Maybe CoreSyn.CoreBndr] -- ^ The InitState - -> [Maybe CoreSyn.CoreExpr] -- ^ The TestInput - -> Bool -- ^ Is it stateful (in case InitState is not specified) + -> [EntitySpec] -- ^ The entities to generate -> IO [(AST.VHDLId, AST.DesignFile)] -moduleToVHDL env cores top init test stateful = do - let topEntity = Maybe.catMaybes top - case topEntity of - [] -> error "Top Entity Not Found" - [topEnt] -> do - let initialState = Maybe.catMaybes init - let isStateful = not (null initialState) || stateful - let testInput = Maybe.catMaybes test - uniqSupply <- UniqSupply.mkSplitUniqSupply 'z' - let all_bindings = concat (map (\x -> CoreSyn.flattenBinds (HscTypes.cm_binds x)) cores) - let testexprs = case testInput of [] -> [] ; [x] -> reduceCoreListToHsList x - let (normalized_bindings, test_bindings, typestate) = normalizeModule env uniqSupply all_bindings testexprs [topEnt] [isStateful] - let vhdl = createDesignFiles typestate normalized_bindings topEnt test_bindings - mapM (putStr . render . Ppr.ppr . snd) vhdl - return vhdl - xs -> error "More than one topentity found" +moduleToVHDL env cores specs = do + (vhdl, count) <- runTranslatorSession env $ do + let all_bindings = concatMap (\x -> CoreSyn.flattenBinds (HscTypes.cm_binds x)) cores + -- Store the bindings we loaded + tsBindings %= Map.fromList all_bindings + let all_initstates = concatMap (\x -> case x of (_, Nothing, _) -> []; (_, Just inits, _) -> inits) specs + tsInitStates %= Map.fromList all_initstates + test_binds <- catMaybesM $ Monad.mapM mkTest specs + let topbinds = Maybe.catMaybes $ map (\(top, _, _) -> top) specs + vhdl <- case topbinds of + [] -> error "Could not find top entity requested" + tops -> createDesignFiles (tops ++ test_binds) + count <- get tsTransformCounter + return (vhdl, count) + mapM_ (putStr . render . Ppr.ppr . snd) vhdl + putStr $ "Total number of transformations applied: " ++ (show count) ++ "\n" + return vhdl + where + mkTest :: EntitySpec -> TranslatorSession (Maybe CoreSyn.CoreBndr) + -- Create a testbench for any entry that has test input + mkTest (_, _, Nothing) = return Nothing + mkTest (Nothing, _, _) = return Nothing + mkTest (Just top, _, Just input) = do + bndr <- createTestbench Nothing cores input top + return $ Just bndr + +-- Run the given translator session. Generates a new UniqSupply for that +-- session. +runTranslatorSession :: HscTypes.HscEnv -> TranslatorSession a -> IO a +runTranslatorSession env session = do + -- Generate a UniqSupply + -- Running + -- egrep -r "(initTcRnIf|mkSplitUniqSupply)" . + -- on the compiler dir of ghc suggests that 'z' is not used to generate + -- a unique supply anywhere. + uniqSupply <- UniqSupply.mkSplitUniqSupply 'z' + let init_typestate = TypeState builtin_types [] Map.empty Map.empty env + let init_state = TranslatorState uniqSupply init_typestate Map.empty Map.empty 0 Map.empty Map.empty Map.empty 0 + return $ State.evalState session init_state -- | Prepares the directory for writing VHDL files. This means creating the -- dir if it does not exist and removing all existing .vhdl files from it. @@ -130,6 +137,6 @@ writeVHDL dir (name, vhdl) = do -- Find the filename let fname = dir ++ (AST.fromVHDLId name) ++ ".vhdl" -- Write the file - Language.VHDL.FileIO.writeDesignFile vhdl fname + FileIO.writeDesignFile vhdl fname -- vim: set ts=8 sw=2 sts=2 expandtab: