X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fc%CE%BBash.git;a=blobdiff_plain;f=HighOrdAlu.hs;h=8467c38d92ad815bc55053937a5445aac4a0f01f;hp=e5dcbfddfd22eb96021e03315b462d41c16dcef6;hb=HEAD;hpb=4a1b18cd81cebb66c95cc0ca8a6aaa441bee1418

diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs
index e5dcbfd..8467c38 100644
--- a/HighOrdAlu.hs
+++ b/HighOrdAlu.hs
@@ -6,28 +6,7 @@ import qualified Prelude as P
 import CLasH.HardwareTypes
 import CLasH.Translator.Annotations
 
-constant :: NaturalT n => e -> Op n e
-constant e a b = copy e
-
-invop :: Op n Bit
-invop a b = map hwnot a
-
-andop :: (e -> e -> e) -> Op n e
-andop f a b = zipWith f a b
-
--- Is any bit set?
---anyset :: (PositiveT n) => Op n Bit
-anyset :: NaturalT n => (e -> e -> e) -> e -> Op n e
---anyset a b = copy undefined (a' `hwor` b')
-anyset f s a b = constant (f a' b') a b
-  where 
-    a' = foldl f s a
-    b' = foldl f s b
-
-xhwor = hwor
-
-type Op n e = (Vector n e -> Vector n e -> Vector n e)
-type Opcode = Bit
+import HighOrdAluOps
 
 {-# ANN sim_input TestInput#-}
 sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))]
@@ -49,4 +28,4 @@ actual_alu :: (Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8)) -> Vect
 --actual_alu = alu (constant Low) andop
 actual_alu (opc, a, b) = alu (anyset (+) (0 :: SizedInt D8)) (andop (-)) opc a b
 
-runalu = P.map actual_alu sim_input
\ No newline at end of file
+runalu = P.map actual_alu sim_input