X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fc%CE%BBash.git;a=blobdiff_plain;f=Alu.hs;h=7171a6549d4a216f7ffb876eacdc4d8db5e22571;hp=ca2dbe9180613a3db75b55843660299246f809aa;hb=HEAD;hpb=acb620510e3623e8dfd979a8b732babd19086a9b

diff --git a/Alu.hs b/Alu.hs
index ca2dbe9..7171a65 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -1,11 +1,16 @@
-module Alu  where
-import Bits
+module Alu where
 import qualified Sim
+import CLasH.HardwareTypes hiding (fst,snd)
+import CLasH.Translator.Annotations
+import qualified Prelude as P
+
+fst (a, b) = a
+snd (a, b) = b
 
 main = Sim.simulate exec program initial_state
 mainIO = Sim.simulateIO exec initial_state
 
-dontcare = DontCare
+dontcare = Low
 
 program = [
             -- (addr, we, op)
@@ -17,67 +22,60 @@ program = [
           ]
 
 --initial_state = (Regs Low High, Low, Low)
-initial_state = ((Low, High), Low, Low)
+initial_state = State (State (0, 1), 0, 0)
 
+type Word = SizedWord D4
 -- Register bank
-
 type RegAddr = Bit
-type RegisterBankState = (Bit, Bit)
+type RegisterBankState = State (Word, Word)
 --data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
 
+{-# NOINLINE register_bank #-}
 register_bank :: 
-  (RegAddr, Bit, Bit) -> -- (addr, we, d)
-  RegisterBankState -> -- s
-  (RegisterBankState, Bit) -- (s', o)
-
-register_bank (Low, Low, _) s = -- Read r0
-  --(s, r0 s)
-  (s, fst s)
-
-register_bank (High, Low, _) s = -- Read r1
-  --(s, r1 s)
-  (s, snd s)
+  RegAddr -- ^ Address
+  -> Bit -- ^ Write Enable
+  -> Word -- ^ Data
+  -> RegisterBankState -> -- State
+  (RegisterBankState, Word) -- (State', Output)
 
-register_bank (addr, High, d) s = -- Write
-  (s', dontcare)
+register_bank addr we d (State s) = (State s', o)
   where
-    --Regs r0 r1 = s
-    (r0, r1) = s
-    r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
-    r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
-    --s' = Regs r0' r1'
-    s' = (r0', r1')
+    s' = case we of
+      Low -> s -- Read
+      High -> -- Write
+        let
+          (r0, r1) = s
+          r0' = case addr of Low -> d; High -> r0
+          r1' = case addr of High -> d; Low -> r1
+        in (r0', r1')
+    o = case we of
+      -- Read
+      Low -> case addr of Low -> fst s; High -> snd s
+      -- Write
+      High -> 0 -- Don't output anything useful
 
 -- ALU
 
 type AluOp = Bit
 
-alu :: AluOp -> Bit -> Bit -> Bit
-alu High a b = a `hwand` b
-alu Low a b = a `hwor` b
+alu :: AluOp -> Word -> Word -> Word
+{-# NOINLINE alu #-}
+--alu High a b = a `hwand` b
+--alu Low a b = a `hwor` b
+alu High a b = a + b
+alu Low a b = a - b
 
-salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
-salu High a b s = (s, a `hwand` b)
-salu Low a b s = (s, a `hwor` b)
-
-type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (Bit))
+type ExecState = State (RegisterBankState, Word, Word)
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
 
+{-# ANN exec TopEntity #-}
 -- Read & Exec
-exec (addr, Low, op) s =
-  (s', z')
+exec (addr, we, op) (State s) =
+  (State s', z')
   where
     (reg_s, t, z) = s
-    (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+    (reg_s', t') = register_bank addr we z reg_s
     z' = alu op t' t
     s' = (reg_s', t', z')
 
--- Write
-exec (addr, High, op) s =
-  (s', dontcare)
-  where
-    (reg_s, t, z) = s
-    (reg_s', _) = register_bank (addr, High, z) reg_s
-    s' = (reg_s', t, z)
-
 -- vim: set ts=8 sw=2 sts=2 expandtab: